STM32 concept

Concept

Cotex-M Core & Cortex-M MCU

The kernel is only the architecture of the CPU, and the MCU is a specific package implementation. CM3-> Cortex-M3.

Memory map

1. 0x0000 0000~ 0x1FFF FFFFIs the code snippet. DETAILED split follows:
   
   0x0800 0000an internal FLASHstart address, this is the place of programming code. System MemoryYes bootloader(ROM). bootloaderThe code can be uploaded via other peripherals (USART, USB). Option bytesThe middle is to configure MCUsome flag bits.

2. 0x2000 0000It is the internal SRAMstart address. Internal SRAMdue to chip manufacturers differ in size. So its end address will also be different.

3. 0x4000 0000It is the start address of the peripheral register. Because some peripheral ports only occupy one to two bits in a register, atomic operationsimultaneous operations cannot be used in multiple processes . ARMThe use of bit-bandingtechnology. It is to map different register bits under the same address into a single address, which is convenient for multi-process operation.

Interrupt & Exception

Processing function: Exception Handler--> Exception; Interrupt Service Routine(ISR) --> Interrupt.

Priority Management is in NVICthe.

SysTimer

Cortex-MIt provided SysTickas a system clock. Can be used to:

1. Provide periodic interrupts for RTOS for scheduling purposes.
2. Provide accurate timing function.

CMSIS

Cortex Microcontroller Software Interface Standard (CMSIS) is the standard software interface of the Cortex-M series.

However, due to different hardware platforms, migration is still very difficult.

bibliography:

1. Mastering STM32 by Carmine Noviello.