#Today is also a day for salted fish~
Robei Cup
In the Robei Cup contest question, there is a sentence that says:
From here, Robei officially hopes that the contestants can use FPGA to build a RISC-V architecture CPU to control the control module. In the integrated circuit competition-Robei Cup (Blind) Interpretation , I briefly introduced the architecture of RISC-V, and also explained why this architecture competition was used.
Then I found that what I said was not very clear, and I just copied the definition, which is actually useless for understanding and use. (I actually didn't plan to use this architecture to write in the beginning. I just thought about writing the control module in Verilog, but I looked at the extra points. I gave in.)
So, I started to get started with RISC-V programming. I checked the information for an afternoon + evening, and then it was very broken. Why should I report this game? Knowledge is not in my head.
—————————————— Caiji doubts the dividing line of life————————————
RISC-V introduction
RISC-V is an open source instruction set CPU architecture that has been very popular in China in the past two years. The instruction set itself was developed by the team at Berkeley University. This architecture is free and open source, but this is not the reason for its popularity. This architecture is described as "simple" in one word, the instruction set is streamlined, and the development process is relatively easy.
In the development of IC, backward compatibility has always been a troublesome issue, in order to ensure the backward compatibility of the architecture