Systemverilog (Green Book) Chapter 4-Connection Design (2) Sampling and Data Drive

In the behavior of simulation, in order to avoid the timing competition problem of the clock and the driving signal in the sequential circuit as much as possible, we need to try to clarify the driving timing and sampling timing.

By default, the clock adds a small wireless delta-cycle to the drive of the combined circuit , the delay between the drive signal and the driven signal . It is smaller than the minimum time unit accuracy.

During the simulation, enter the command "run 0", which is to let the simulation run for a delta-cycle time.

timescale 1ns/1ns
module racel;

bit clk1,clk2;
bit rstn;
logic [7:0] d1;

initial begin     //产生时钟clk1
    forever #5 clk1 <= !clk1;
end

//产生时钟clk2
always @(clk1) clk2 <= clk1;

initial begin 
    #10 rstn <= 0;
    #20 rstn <= 1;

end

//计数器
always @(posedge clk1, negedge rstn) begin
    if(!rstn) d1<= 0;
    else      d1<= d1 + 1;
end

//在clk1,clk2上升沿打印出d1的数值

always @(posedge clk1) $display("%0t ns d1 value is 0x%0x", $time,d1);

always @(posedge clk2) $display("%0t ns d1 value is 0x%0x", $time,d1);

endmodule

Question: At 45ns, the sampled d1 value is 1, so what is the sampled d1 value at clk2 at 45ns? 2

Due to various possibilities, if there are only a few delta-cycle delays between the clk and the sampled data, there may be problems with the sampling. In the above example, clk1 and clk2 sample d1, and different samples are obtained at the same time. result.

How to avoid this problem:

(1) When driving, add artificial delay to simulate the real delay behavior, and increase the delay drive between clk and variables to improve the accuracy of the DUT signal and the reliability of the TB sampling signal.

(2) In addition, for some sampling, there is still a delta-cycle problem, we can also sample at a certain time of the sampling event to simulate the sampling requirements at the time of establishment to ensure the reliability of sampling.

 

Clock block problem:

clocking bus @(posedge clock1);
    default input #10ns output #2ns;
    input data ,ready , enable;
    output negedge ack;
    input #1step addr;
endclocking

Note that adding the clock block should also address the following issues:

(1) The clocking block can be defined not only in the interface, but also in the module and program;

(2) The signals listed in clocking are not defined by yourself, but are defined by the interface or other declaration clocking module;

(3) After the declaration of clocking, it is accompanied by the default sampling event, otherwise it defaults to the first 1step input sampling and the latter # 0 output driver;

(4) You can also overwrite the default event with a new sampling event.

module clocking
    bit vld;
    bit grt;
    bit clk;
    clocking ck #(posedge clk);
        default input #3ns output #3ns;
        input vld;
        output grt;
    endclocking

initial forever #5ns clk <=!clk;

//驱动
initial begin: drv_vld
    $display("$%0t vld is assigned %d", $time,vld);
    #3ns vld =1; $display("$%0t vld is assigned %d", $time, vld);
    #10ns vld =0; $display("$%0t vld is assigned %d", $time, vld);
    #8ns vld =1; $display("$%0t vld is assigned %d", $time, vld);
end

//采样1，时钟上升沿采样
initial forever
    @ck $display("$%0t vld is sampled as %d at sampling time $%0t", $time, vld ,$time);

//采样2，等到ck事件即时钟上升沿利用clocking块采样
initial forever
    @ck $display("$%0t ck.vld is sampled as %d at sampling time $%0t", $time, ck.vld ,$time-3);                //等到ck事件即时钟上升沿利用clocking块采样
endmodule

This topic examines the difference between direct sampling clock rising edge sampling and clocking block sampling:

 

It can be seen from the figure that the sampling value obtained by directly sampling the rising edge of the clock is 101; and the value obtained by sampling the clock block is 001.

module clocking
    bit vld;
    bit grt;
    bit clk;
    clocking ck #(posedge clk);
        default input #3ns output #3ns;
        input vld;
        output grt;
    endclocking

initial forever #5ns clk <=!clk;

//驱动
initial begin: drv_grt
    $display("$%0t grt initial value is %d", $time,grt);
    @ck ck.grt <=1; $display("$%0t grt is assigned 1", $time);
    @ck ck.grt <=0; $display("$%0t grt is assigned 0", $time);
    @ck ck.grt <=1; $display("$%0t grt is assigned 1", $time);
end


initial forever
    @grt $display("$%0t grt is sampled as %d", $time,grt);

endmodule

Analyzing the output will reveal that there is a 3ns delay between the actual drive output and the output set by the simulation.

 

to sum up:

(1) In order to avoid the problem of sampling competition, a fixed delay should be added to the driving link of the verification environment , so that the timing between the clock and the driven signal is more easily reflected in the simulated waveform, which is convenient for accurate DUT processing and accurate TB sampling.

(2) If the TB is sampling the data sent from the DUT, and there is a delta-cycle between the clock and the driven signal, it should be considered to simulate the setup and hold time at the earlier time of the clock sampling edge , so as to avoid sampling due to Sampling competition problems caused by delta-cycle. 

(3) Apply clockiing to interface to declare the driving relationship between each interface and clock sampling, which can greatly improve the accuracy of data driving and sampling and eliminate the possibility of sampling competition.