一、平台:msm8953 android 7.1.2 主要参考高通文档
设备树：kernel/msm-3.18/arch/arm/boot/dts/qcom/msm8953.dtsi
usb3: ssusb@7000000{
compatible = "qcom,dwc-usb3-msm";
reg = <0x07000000 0xfc000>,
<0x0007e000 0x400>;
reg-names = "core_base",
"ahb2phy_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts = <0 136 0>, <0 220 0>, <0 134 0>;
interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
USB3_GDSC-supply = <&gdsc_usb30>;
qcom,usb-dbm = <&dbm_1p5>;
qcom,msm-bus,name = "usb3";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<61 512 0 0>,
<61 512 240000 800000>;
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
<&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>,
<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
<&clock_gcc clk_gcc_usb30_sleep_clk>,
<&clock_gcc clk_xo_dwc3_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;
clock-names = "core_clk", "iface_clk", "utmi_clk",
"sleep_clk", "xo", "cfg_ahb_clk";
dwc3@7000000 {
compatible = "snps,dwc3";
reg = <0x07000000 0xc8d0>;
interrupt-parent = <&intc>;
interrupts = <0 140 0>;
usb-phy = <&qusb_phy>, <&ssphy>;
tx-fifo-resize;
snps,usb3-u1u2-disable;
snps,nominal-elastic-buffer;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
};
此处省略.......................
};
qcom,dwc-usb3-msm 对应kernel/msm-3.18/drivers/usb/dwc3/dwc3-msm.c
snps,dwc3 对应 对应kernel/msm-3.18/drivers/usb/dwc3/core.c //根节点
二、初始化
由于根节点与dwc3-msm驱动程序相对应，因此首先将其初始化。 该驱动程序的probe回调负责：
1、初始化特定于驱动程序的资源
工作队列– chg_work，id_work，resume_work等（特定于平台）
2、初始化并启用USB内核所需的时钟
Xo_clk，iface_clk，sleep_clk等（特定于平台）
3、初始化regulators，HSPHY和SSPHY
初始化和注册驱动程序特定的IRQ处理数的IRQ
4、将设备注册到PM运行时层
5、注册和设置公交车比例为SNOC
6、读出DTSI参数和填充相应的变量
DWC3 MSM驱动程序仅负责处理任何特定于MSM的设置和资源。
三、中断
The DWC3 MSM driver only has two interrupt handlers in the driver, which service:USB asynchronous interrupts –hs_phy_irq; RISING edge triggered
PMIC ID interrupts –pmic_id_irq; DUAL edge triggered
hs_phy_irq() is primarily used to wake up the controller when it is suspended after an HSPHY asynchronous interrupt occurs.
The pmic_id_irq() handler is used to notify of the ID ground and ID float events, and propagatesthis to the DWC3 OTG driver
四、HCD driver initialization
dwc3_host_init() is responsible for setting up the necessary resources for the platform to run in
host mode.
dwc→xhci – Holds the platform_device allocated for the XHCI HCD. The dwc3_host_init()
calls platform_device_add() that probes the respective XHCI HCD driver.
Pdata.vendor – Carries the vendor ID
Pdata.revision – Carries the DWC hardware revision
dwc→xhci_resources – Has the I/O resources and controller base addresses when adding the
platform device
Adding the XHCI platform device
For the XHCI controller driver to initialize correctly, it requires the minimum platform data fields
to be set correctly. At least the resources must be added to the platform device structure, and the
DWC3 XHCI-related parameters such as “vendor” and “revision” are optional, thus it is part of
platform data.
During the dwc3_probe() call, XHCI resources are populated with the IRQ resource along with
the controller memory address and range. This is used later on when the platform device is added.
五、DWC3 otg状态机介绍
The OTG state machine is simplified to five states. The OTG states are:
OTG_STATE_UNDEFINED – This state is only valid at first boot up. After the device
moves to OTG_STATE_B_IDLE, this state is no longer valid.
OTG_STATE_B_IDLE – This state is the default state of the OTG state machine. It has logic
to handle both ID and BSV events.
OTG_STATE_B_PERIPHERAL – This state occurs when the device acts in device mode.
OTG_STATE_A_IDLE – This is a transition state into host mode after the USB ID is
grounded. It attempts to start the host stack before continuing.
OTG_STATE_A_HOST – This state occurs when the device acts in host mode.
It also services the following state machine bits:
B_SESS_VLD – B Session Valid
ID – ID status
六、otg状态机流程
1. During bootup, the charger driver attains a reference to the USB power supply using
power_supply_get_by_name().
2. After the charger driver has a reference to the USB power supply, it can notify the USB
driver of a VBUS event through qpnp_chg_usb_usbin_valid_irq_handler().
3. The USBIN valid IRQ uses power_supply_set_present(), which has a registered callback of
dwc3_msm_power_set_property_usb() in the USB driver.
4. The USB driver sets mdwc→ext_xceiv.bsv to the value passed, which informs whether
VBUS is high or low.
5. dwc3_msm_power_set_property_usb() queues a delayed work to the resume_work work
queue (delay = 20 ms).
6. dwc3_resume_work() resumes the controller (if needed) using pm_runtime_get_sync() on
mdwc→dev.
7. The dwc3_resume_work() executes the hook to notify the DWC OTG driver of an external
event (dwc3_ext_event_notify()).
8. dwc3_ext_event_notify() handles setting/clearing the BSV state machine bit, and schedules
work for the OTG state machine. (The event passed from resume_work is
DWC3_EVENT_XCEIV_STATE.)
9. dwc3_otg_sm_work() runs to service the BSV change (start/stop device stack).
USB controller-based
The USB controller-based VBUS detection mechanism is similar to the PMIC-based sequence.
Only the detection is different and is handled within the DWC OTG driver. It does not involve
any communication with the DWC MSM driver.
The following process describes the USB controller-based sequence flow:
1. The DWC3 controller has a separate interrupt line for handling ID/BSV events. The
registered IRQ handlers for these events are dwc3_otg_interrupt().
2. The dwc3_otg_interrupt() handler would be responsible for setting/clearing the BSV bit,
which replaces dwc3_ext_event_notify() in the PMIC-based detection.
3. After the correct state bits are set, the IRQ handler schedules for the
dwc3_msm_otg_sm_work() to run. The next steps are identical to the PMCI-based sequence.
