有时,我们遇到一些情况,我们希望求解器从众多语句中随机选择一个。 关键字randcase引入了一个case语句,该语句随机选择其分支之一。 案例项目表达式是正整数值,代表与每个项目相关的权重。 选择某项商品的可能性由该商品的权重除以所有权重之和得出。
Syntax
randcase
item : statement;
...
endcase
例
所有权重的总和为9,因此选择第一个分支的概率为1/9或11.11%,选择第二个分支的概率为5/9或55.56%,选择最后一个分支的概率为3 / 9或33.33%。
module tb;
initial begin
for (int i = 0; i < 10; i++)
randcase
1 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule
Simulation Log
ncsim> run
Wt 5
Wt 5
Wt 3
Wt 5
Wt 1
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
ncsim: *W,RNQUIE: Simulation is complete.
请注意,出现次数最多的是5次,而出现次数最少的是1次,介于两者之间的次数为3次。
如果分支指定权重为零,则不采用该分支。
module tb;
initial begin
for (int i = 0; i < 10; i++)
randcase
0 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule
Simulation Log
ncsim> run
Wt 5
Wt 5
Wt 3
Wt 5
Wt 5
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
ncsim: *W,RNQUIE: Simulation is complete.
如果所有randcase_items指定零权重,即使这样做没有任何意义,那么也不会进行任何分支,并且可能会导致运行时警告。
module tb;
initial begin
for (int i = 0; i < 10; i++)
randcase
0 : $display ("Wt 1");
0 : $display ("Wt 5");
0 : $display ("Wt 3");
endcase
end
endmodule
Simulation Log
ncsim> run
ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
File: ./testbench.sv, line = 4, pos = 14
Scope: tb.unmblk1
Time: 0 FS + 0
ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
File: ./testbench.sv, line = 4, pos = 14
Scope: tb.unmblk1
Time: 0 FS + 0
ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
File: ./testbench.sv, line = 4, pos = 14
Scope: tb.unmblk1
Time: 0 FS + 0
...
参考文献:
【1】https://www.chipverify.com/systemverilog/systemverilog-randcase