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# 1）Verilog Coding Style For Improved Simulation Efficiency
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Simulation Efficiency: Memory & Time
Simulation efficiency should not be the only Verilog coding criteria
Code readability, simulation accuracy, displaying diagnositic information and so on.
|
|
Good |
Bad |
| 3 |
case |
if/else-if |
| 4 |
no extra begin end |
with extra begin end |
| 5 |
define |
parameredef defparam |
| 6 |
grouping of assignments within one always blocks |
|
| 7 |
no ports |
ports |
| 8 |
1ns/1ns |
1ns/1ps |
| 9 |
no needless $time |
needless $time |
| 10 |
behavioral clock osc |
gate clock osc |
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# 2）《Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!》
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Introduction: A Verilog race condition occurs when two or more statements that are scheduled to execute in
the same simulation time-step, would give different results when the order of statement
execution is changed, as permitted by the IEEE Verilog Standard.
Guideline #1: When modeling sequential logic, use nonblocking assignments.
Guideline #2: When modeling latches, use nonblocking assignments.
Guideline #3: When modeling combinational logic with an always block, use blocking assignments.
Guideline #4: When modeling both sequential and combinational logic within the same always block, use nonblocking assignments.
Guideline #5: Do not mix blocking and nonblocking assignments in the same always block.
Guideline #6: Do not make assignments to the same variable from more than one always block.
Guideline #7: Use $strobe to display values that have been assigned using nonblocking assignments.
Guideline #8: Do not make assignments using #0 delays.
Conclusion: Following the above guidelines will accurately model synthesizable hardware while
eliminating 90-100% of the most common Verilog simulation race conditions.
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# 3）《Verilog Nonblocking Assignments With Delays, Myths & Mysteries》
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A) guidelines for chossen of blocking assignment type
same with that in《Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!》
Bergeron makes the observation that he had "yet to see a single testbench that simulates with
identical results on Verilog-XL and VCS[9]." I believe Bergeron is following the wrong
guidelines.
When following the guidelines presented in this paper, except when there have been simulator
bugs, I have yet to see a testbench simulate differently between any two major Verilog simulators.
B) delay in nonblocking assignment
Based on the above observations, I still prefer the simplicity of coding nonblocking assignments
with no delays. If delays are later required for mixed RTL and gates simulations, I can add the
required nonblocking assignment delays to the outputs of my models (the only place where it is
really required for correct simulation) or I can quickly open my design files and globally substitute
/<=/<= `D/ and add the conditional `D macro definition (basically I am lazy and can fix mixed
The alternate and equally valid strategy is to add conditional `D macro definitions right from the
start of a project to all RTL models. This strategy will help avoid 90%+ of the potential mixed
simulation problems that might occur in the future. It is also an easy coding guideline to impose
on the less-Verilog-educated masses. Keep in mind that a #1 delay is not always enough to fix all
mixed simulation problems.
Engineers could avoid coding most nonblocking assignment #1 delays if VCS and other leading
simulator-vendors would implement a +nba1 command line switch to automatically add #1
delays to all no-delay nonblocking assignments in sequential always blocks.
The +nba1 switch could assist engineers to easily detect simulation problems related to deficient
vendor models, skewed clock delays or mixed RTL and gate-level simulations. This switch would
prove a valuable debugging tool in large, mixed, system simulation environments.
