RTL Coding 读书笔记2：Synthesis

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# 1) RTL coding styles that yield simulation and synthesis mismathes
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casex              dont use           mistake for "dontcase or X-state?" 
full_case          better not use    mannully confirm no latch
parallel_case    better not use    mannully confirm no overlapping

function            be careful          mannully confirm no atch
casez & ?         useful               take care of open wires

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# 2) full_case parallel_case, the evil twins of Verilog Synthesis
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if-else-if	model priority encoder
case	model true-table-like structure
case	examine all synthesis toll case-statement report
casez	caution ! used with "?" Insead of "z" zto model dont-care
casex	dont use in synthesizable code
full_case parallel_case	in general, dont use can be used for one-hot FSM