module Freq_divider #(parameter N = 27) ( input clk, input rst, output [N-1:0]freq_div, output count ); reg [N-1:0]regN = 0; always@(posedge clk) begin if(rst) regN <= 0; else regN <= regN+1; end assign freq_div = regN; assign count = (regN == 2**N-1)?1'b1:1'b0; endmodule module Digital_decode ( input clk, input [3:0]data, output [7:0]Trans_num ); reg [7:0]reg_Trans_num = 0; always@(posedge clk) begin case(data) 4'd0: reg_Trans_num <= 8'b0000_0011; 4'd1: reg_Trans_num <= 8'b1001_1111; 4'd2: reg_Trans_num <= 8'b0010_0101; 4'd3: reg_Trans_num <= 8'b0000_1101; 4'd4: reg_Trans_num <= 8'b1001_1001; 4'd5: reg_Trans_num <= 8'b0100_1001; 4'd6: reg_Trans_num <= 8'b0100_0001; 4'd7: reg_Trans_num <= 8'b0001_1111; 4'd8: reg_Trans_num <= 8'b0000_0001; 4'd9: reg_Trans_num <= 8'b0000_1001; default: reg_Trans_num <= 8'b0001_0001; endcase end assign Trans_num = reg_Trans_num; endmodule
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