SV——在Verilog和SV的block中定义局部变量

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0. 介绍

在Verilog和systemverilog中的begin..end和fork..join block中都可以定义局部变量。但有区别。

1. Verilog

Verilog allows local variables to be declared in named begin...end and
fork...join blocks. These variables can be referenced hierarchically, using the
block name as part of the hierarchical path.

module ehip_vlog_style (... );
    always @(posedge elk)
        for (i=O; i<=15; i=i+l) begin: loop
        integer temp;
    end
endmodule

module test;
    II named block
    II local variable
    ehip_vlog_style dut (... );
    initial $display ("temp = %Od", test.dut.loop.temp); II OK
endmodule

2. System Verilog

SystemVerilog simplifies Verilog by allowing local variables to be declared in
unnamed begin...end and fork...join blocks.

module ehip_sv_style (... );
    always_ff @(posedge elk)
        for (int i=O; i<=15; i++) begin
        integer temp;
    end
endmodule

program automatic test;
    Verilog and SystemVeriiog Gotchas
    chip_sv_style dut (... );
    initial $display ("temp = %Od", test.dut.temp); II GOTCHA!
endmodule

3. reference

《Verilog and SystemVerilog Gotchas》