Applications Subsystem Firmware Processor Developer Processor DMA Controller
Bluetooth Subsystem Processor Subsystem Digital Baseband Bluetooth Radio
Audio Subsystem Qualcomm® Kalimba™ DSP *2 Subsystem Clocking Audio Engine
Host Interfaces Subsystem UART I²C / SPI FS PHY
PMU Subsystem SMPSs and LDOs Auxiliary ADC Li-ion Battery Charger
System Manager Firmware Processor
Boot Manager OTP Memory
PIO Controller Developer/QTIL Firmware
PCB design
35 μm thick (1 oz) copper lands are recommended
nonsolder mask defined (NSMD) lands (lands smaller than the solder mask aperture) are preferred because of the greater accuracy of the metal definition process compared to the solder mask process
Bluetooth subsystem
Receiver ：32 MHz processor
The receiver consists of an LNA
Transmitter ：EDR2 and EDR3
a nonlinear PA is usable he PA is a Class-D design
Crystal oscillator
Frequency stability ±15ppm
Crystal ESR, 32 MHz 25Ω
Load Capacitance 6pF
Device fine load capacitance step 0.025pF
Input signal 0.4-1.2V
System power states
No Power
Active
Shallow Sleep a subsystem can turn off or reduce the frequency of clocks and/or power down memories.
Deep Sleep VDD_DIG_CORE
events can move QCC5124 VFBGA to Active state (selectable via software) from Deep Sleep state
■ A rising edge on SYS_CTRL■ A rising edge or a falling edge on VCHG■ Activity on any PIO
■ Activity on any digital interface■ A timer■ Digital activity on any LED pads (when configured as a digital input)
■ Activity on the debug interfaces■ USB device resume
Dormant ■ A rising edge on SYS_CTRL ■ A rising edge or a falling edge on VCHG ■ Activity on any PIO[8:1] ■ A timer
Off ■ A rising edge on SYS_CTRL held high for 20 ms ■ A rising edge on VCHG held high for 20 ms
Host Interfaces subsystem
HCI是一个抽象的标准的蓝牙通讯接口，在基于HCI协议调用BCCMD时，需要在Bluez已经建立好hci接口的基础上使用。
BCSP（Bluecore Serial Protocol）是CSR自己制定的传输层协议，主要目的是用来加强在没有使用CTS、RTS进行流量控制的情况下进行可靠的数据传输的能力。其概念是 相对H3 , H4而言。
UART Supports H4 and BCSP HCI interfaces or raw UART to application
Applications subsystem
2 x 32/80 MHz central processing unit (CPU) cores using Kalimba DSP architecture
32‑bit reduced instruction set computer (RISC) core with DSP features, integrated for optimal control code execution
Private data RAM, 32 KB on Developer processor
2-way cache 16 KB on Developer processor
8 KB of tightly coupled memory on Developer processor
32 KB shared buffer RAM
Audio subsystem
120/80/32 MHz for audio processing
Program ROM: 5 Mb Program RAM and caches 80 KB of program RAM implemented as 10 banks of 8 KB each
Data RAM size: 256 KB
differential Class-AB audio outputs or differential high efficiency Class-D
Audio MCLK: Programmable, available on PIO[15]
2 Codec output channels, 6 Codec input channels supporting
Digital mics 6 mono/3 stereo Supports 500 kHz, 1, 2, 4 MHz clock frequencies
BAC Buffer Access Controller The BAC implements operations to manipulate audio buffer data to save DSP MIPs.
ANC
Q&A
遇到的困惑写出来分享一下。
1. ANC为什么只针对2kHz以下的低频噪音？
一方面，耳机的物理隔音方式（被动降噪）可以有效阻挡高频噪音，没必要用ANC降高频噪声。另一方面，低频噪声波长较长，可以承受一定的相位延迟，而高频噪声波长短，对相位偏差敏感，因此ANC消高频噪声并不理想。
2. 当electronic delay比primary delay大时，算法性能大大下降如何理解？
P(z)延时小，S(z)延时大，比如P(z)=z-1, S(z)=z-2，只有当W(z)=z才能满足要求，非因果，unreachable。
3. Feedforward ANC、narrow-band feedforward ANC、feedback ANC有什么区别？
Feedforwad结构有一个ref mic和一个error mic，分别采集外部噪音和内部残差信号。feedback结构只有一个error mic，由error mic和adaptive filter output生成reference signal。
Broad-band feedforward就是上面所述结构，而narrow-band结构中，noise source会产生某个signal触发signal generator，signal generator再生成reference signal送给adaptive filter。只适用于消除periodic noise。
Feedback ANC由于只有error mic，用error mic来恢复feedforward结构中ref mic采集的信号，通路不满足因果约束，因此只消除predictable noise components，即窄带周期性噪声。需要注意的是，feedforward如果不满足因果约束，即electronic delay比主通道acoustic delay长的话，也只能消除窄带周期性噪声。
另外还有一种Hybrid ANC的结构，同时包含feedforward和feedback结构，主要的优点是可以节省自适应滤波器的阶数。
Audio interfaces
Inputs should be AC coupled, typically with a 2u2 capacitor. This capacitor value can be reduced at the expense of low frequency response attenuation.
Stereo differential input 0xC6 single ended input, using the P inputs 0xA5 using the N inputs 0x14A
Line/Mic inputs
0 dB gain the maximum input is 2.4 Vpp
Inputs should be AC coupled, typically with a 2.2 μF capacitor.
QCC5124 VFBGA has a microphone bias source, capable of biasing two external analog microphones at a load current of up to 3 mA.
Line/Headphone outputs
Class-D is a high efficiency, switching mode amplifier. The secondary Class-AB is a linear amplifier, and consumes more power.
Audio MCLK page 45
Simultaneous audio routing
Codec inputs
only codec input A B Analog A-F all have Digital
Audio slots
Stereo I²S 2 PCM 2/4 Analog ADC 2 Analog DAC 2 Digital microphone ·
Peripheral interfaces
20 PIO pads: 1 x Reset (active low) pad: PIO[1] 5 x pads intended for LED operation: LED[5:4, 2:0] Power-on signaling: SYS_CTRL
Digital microphones, SPDIF, UART, Bit Serializer (I²C/SPI), and LED PWM controllers can use any PIO.
Standard I/O
Each VDD_PADS domain can be separately powered, from 1.7 V to 3.6 V.
PIO can be programmed to have a pull-up or pull down with two strengths (weak and strong). PIO can also be programmed with a sticky function where they are strongly pulled to their current input state. PIO have a reset pull state, after reset the pulls can be re-configured by software.
PIO also have a programmable drive strength capability of 2, 4, 8, or 12 mA.
All PIO are readable by all subsystems, but for write access are assigned by software to particular subsystem control. PIO inputs are via Schmitt triggers.
Pad multiplexing
When a PIO is allocated to a particular subsystem, the output is propagated combinationally from the subsystem to the pad. That is, there are no registers between the subsystem and the pad. The LED pins and some other peripheral I/O states can be read as virtual PIO
RESET# reset pin
active low reset QCC5124 VFBGA then requires a SYS_CTRL assertion or VCHG attach to restart.
QTIL recommends that QCC5124 VFBGA is powered down via software-controlled methods rather than external assertion of RESET#.
Holding RESET# low continuously is not the lowest QCC5124 VFBGA power state, because pull downs are enabled on VCHG and VDD_BYP in this state.
RESET# is guaranteed to work if held low for 120 μs.
SYS_CTRL pin
From the OFF state, SYS_CTRL must be asserted for >20 ms to start power up.
SYS_CTRL is VBAT tolerant (4.8 V max), and typically connected via a button to VBAT.
SYS_CTRL has no internal pull resistor, and requires an external pull-down if left undriven.
LED pads
The pad operates as an open-drain pad, tolerable of voltages up to 7.0 V.
Each pad is rated to sink up to 50 mA of current.
Analog input: 10‑bit auxiliary ADC.
Digital / Button input Typically this is used for active high button signals to
ensure that the input returns to 0 when the button is released. The pads are 7.0 V tolerant and the logic 1
threshold is typically 1 V.
USB device port
Extra ESD protection is not required on VCHG (VBUS) because QCC5124 VFBGA meets the USB certification
requirements of a minimum of 1uF, and a maximum of 10 μF being present on VCHG (VBUS).
Transaction bridge
USB3.0 signals can generate noise in the Bluetooth ISM band. For applications where sensitive RF
measurements take place, QTIL recommends connecting TRBI200 using USB2.0.
The TRBI200 USB transaction bridge interface requires power for input/output buffers to be supplied externally. This voltage must match the power supply domain used for the TRB pads (VDD_PADS_1).
Boot Manager
QCC5124 VFBGA contains one-time programmable memory areas, used to hold a 128‑bit customer programmable security key.
System Manager
The System Manager maintains a 1 MHz system timer, which is distributed to the subsystems in the hardware using
the transaction bus. The system time has 20 ppm, 250 ppm, and 20% modes to optimize current in low-power states.
PMU subsystem
■ Internal configuration: Supporting charge rates of 2 mA to 200 mA with no external components required.
■ External configuration: Supporting charge rates of 200 mA to 1800 mA with the addition of one PNP pass device
and external resistor.
Trickle charge Vpre threshold (A) 2.1 V
Charging modes
Headset mode: Speaker mode: