JZ4775是一款针对平板电脑、电子书、移动数字电视等多媒体丰富移动设备的移动应用处理器。该SOC引入了一种创新的架构，既满足了移动多媒体设备对高性能移动计算和高质量视频解码的要求。JZ4775提供高速CPU计算能力和流畅的720p视频重放。
CPU
XBurst® CPU
– XBurst®
RISC instruction set
– XBurst® SIMD instruction set
– XBurst®
FPU instruction set supporting both single and double floating point format which are IEEE754 compatible
– XBurst®
9-stage pipeline micro-architecture, the maximum frequency is 1G
MMU
– 32-entry joint-TLB
– 4 entry Instruction TLB
– 4 entry data TLB
L1 Cache
– 16kB instruction cache
– 16kB data cache
Hardware debug support
16kB tight coupled memory
L2 Cache
– 256kB unify cache
VPU
MPEG-1/2 decoding up to 720P 30fps
VC-1 decoding up to 720P 30fps
H.264 decoding up to 720P 30fps
VP8 decoding up to 720P 30fps
MPEG-4 decoding up to 720P 30fps
RV9 decoding up to 720P 30fps
GPU
X2D
– Location: AHB bus
– Input format
Separate frame: YUV /YCbCr (4:2:0)
Packaged data: RGB888, RGB565, RGB555, NV12, NV21,TileYUV
– Output data format
ARGB888，XRGB888, RGB555, RGB565
– Color convention coefficient: configurable (CSC enable)
– Minimum input image size (pixel): 4x4
– Maximum input image size (pixel): 12288x12288 (12k x 12k )
– Maximum output image size (pixel)
Width : up to 12288
Height: up to 12288
– Image resizing
bi-cube zooming mode
– Image Clockwise 90, 180, 270 rotation
– Image horizontal and vertical mirror , same time with rotation
– 5 layers OSD
Display/Camera/Audio
LCD controller(compress must with IPU direct display )
– Basic Features
Support panel(TFT, SLCD)
Display size up to 1280*720@60Hz(BPP24)
– Colors Supports
Encoded pixel data of 16, 18 or 24 BPP in TFT mode
Support up to 16,777,216 (16M) colors in TFT mode
Support 24 BPP packed data
– Panel Supports
Support 16-bit parallel TFT panel
Support 18-bit parallel TFT panel
Support 24-bit serial TFT panel with 8 data output pins
Support 24-bit parallel TFT panel
Support Delta RGB panel
Support SLCD panel
– OSD Supports
Supports one single color background
Supports two foregrounds, and every size can be set for each foreground
Supports one transparency for the whole graphic
Supports one transparency for each pixel in one graphic
Supports color key and mask color key
Supports porter-duff blending
EPD Controller
– Supports multiple types of compatible EPD panels
– Supports different size up to 4096x4096@20Hz
– Supports 2/3/4 bits grayscale and color display
– Pixel base updating
– Supports hand-writing mode
– Supports SW LUT algorithm
– Supports AUTO-DU, AUTO-GC4 mode
EPD Color Engine
– Input data format is RGB565
– Maximum image direction is 4096x4096
– Includes CSC between RGB888 and YUV444
– CSC supports 601 or 709, Wide or Narrow mode
– Includes 3x3 Color Filter modules for RGB.R, RGB.B, RGB.B and YUV.Y.
– Includes Color Linearization(VEE) for YUV.Y using 256-grade LUT
– Supports Color Correction(HUE) for YUV.UV, and the coefficients are configurable
– Supports Color Saturation for YUV.UV, and the coefficients are configurable
– Supports Dither for RGB.R, RGB.B, RGB.B and YUV.Y. The output format is 2/3/4-bit configurable.
– Supports Color Remapping for RGB.R, RGB.B, RGB.B and YUV.Y. If for RGB, there are two methods can be selected between individual CFA component and pixel array. And, the output order is configurable.
– The EPDCE has a AXI master interface and a AHB slave interface.
Camera interface module
– Input image size up to 2048x2048 pixels
– Max. VGA for image preview
– Max. VGA for video record
– Integrated DMA
– Supported data format: YCbCr 4:4:4, YCbCr 4:2:2 and other formats
– Output format
csc mode: YCbCr 4:2:2 or YCbCr 4:2:0
bypass mode: the input data format
– Output frame format
Packaged : for all data format
Separated: for YCbCr 4:4:4, YCbCr 4:2:2 and YCbCr 4:2:0
– Supports ITU656 (YCbCr 4:2:2) input
– Configurable CIM_VSYNC and CIM_HSYNC signals: active high/low
– Configurable CIM_PCLK: active edge rising/falling
– 256x33 image data receive FIFO (RXFIFO)
– PCLK max. 80MHz
– Configurable output order
AC97/I2S/SPDIF controller
– AC-link (AC97) features
Up to 20 bit audio sample data sizes supported
DMA transfer mode supported
Stop serial clock supported
Programmable Interrupt function supported
Support mono PCM data to stereo PCM data expansion on audio play back
Support endian switch on 16-bits normal audio samples play back
Support variable sample rate in AC-link format
Multiple channel output and double rated supported for AC-link format
Power Down Mode and two Wake-Up modes Supported for AC-link format
– I2S features
8, 16, 18, 20 and 24 bit audio sample data sizes supported, 16 bits packed sample data is supported
DMA transfer mode supported
Stop serial clock supported
Programmable Interrupt function supported
Support mono PCM data to stereo PCM data expansion on audio play back
Support endian switch on 16-bits normal audio samples play back
Internal programmable or external serial clock and optional system clock supported for I2S or MSB-Justified format
Internal I2S CODEC supported
Two FIFOs for transmit and receive respectively
SPDIF features
8, 16, 18, 20 and 24 bit audio sample data sizes supported
DMA transfer mode supported
Stop serial clock supported
Programmable Interrupt function supported
Support IEC60958 two-channel PCM audio
Support IEC61937 multi-channel compressed audio
Support consumer mode and only support transmitter mode
PCM interface
– Data starts with the frame PCMSYN or one PCMCLK later
– Support three modes of operation for PCM
Short frame sync mode
Long frame sync mode
Multi-slot mode
– Data is transferred and received with the MSB first
– Support master mode and slave mode
– The PCM serial output data, PCMDOUT, is clocked out using the rising edge of the
PCMSCLK
– The PCM serial input data, PCMDIN, is clocked in on the falling edge of the PCMSCLK
– 8/16 bit sample data sizes supported
– DMA transfer mode supported
– Two FIFOs for transmit and receive respectively with 16 samples capacity in every direction
Internal CODEC Interface
– 24 bits ADC and DAC
– Headphone load up to 16 Ohm
– Sample frequency supported: 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k, and96k
– Stereo line input
– DAC to HP path: Power consumption: 17.6mW, SNR: 95dB, THD: -65dB @17.6mW /16Ohm
– DAC to stereo line output path @10kOhm: SNR: 95dB A-Weighted, THD: -80dB @FS-1dB
– Line input to ADC path: SNR: 95dB A-Weighted, THD: -80dB @FS-1dB
– Separate power-down modes for ADC and DAC path with several shutdown modes
– Reduction of audible glitches systems: Pop Reduction system, Soft Mute mode
– Output short circuit protection
– Digital MIC supported.
– Support Capacitor-coupled and Capacitor-less mode headphone connection
– Advance SNR of recode.
– Updata AGC system.
– Add digital amplitude limiter use for remove the short when sound is very largely.
– Add DAC digital amplifier the gain up to 32dB
Memory Interface
DDR Controller
– Support DDR2, DDR3, DDR3L, mobile DDR (LPDDR), memory，up to 800Mbps
– Support x16 and x32 external DDR data width
– Asynchornize to system bus and each port.
– Support clock-stop mode
– Support auto-refresh and self-refresh
– Support power-down mode and deep-power-down mode
– Programmable DDR timing parameters
– Programmable DDR row and column address width and order
Static memory interface
– Support 3 external chip selection CS3~1#. Each bank can be configured separately
– The size and base address of static memory banks are programmable
– Direct interface to 8/16-bit bus width external memory interface devices or external static memory to each bank. Read/Write strobe setup time and hold time periods can be programmed and inserted in an access cycle to enable connection to low-speed memory
– Wait insertion by WAIT pin
– Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different banks, or a read access followed by a write access to the same bank
NAND flash interface
– Support on CS3~CS1#, sharing with static memory bank3~bank1
– Support both of conventional NAND flash memory and Toggle NAND flash memory
– Support most types of NAND flashes, 8/16-bit data access, 512B/2KB/4KB/8KB/16KB page size. For 512B page size, 3 and 4 address cycles are supported. For 2KB/4KB/8KB/16KB page size, 4 and 5 address cycles are supported
– Support read/erase/program NAND flash memory
– Support boot from NAND flash
BCH Controller
– Support up to 64-bit ECC encoding and decoding for NAND
The XBurst®processor system supports little endian only
System Functions
Clock generation and power management
– On-chip 24/26MHZ oscillator circuit
– On-chip 32.768KHZ oscillator circuit
– One two-chip phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK, VPU_CLK frequency can be changed separately for software by setting registers
– SSI clock supports 50M clock
– MSC clock supports 100M clock
– Functional-unit clock gating
– Shut down power supply for J1, VPU, L2CC, X2D
Timer and counter unit with PWM output and/or input edge counter
– Provide eight channels, four channels 0~3 can generate PWM, two of them have input signal transition edge counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Every channel has PWM output
OS timer
– One channel
– 32-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA
Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software
PCLK, EXTAL and RTCCLK can be used as the clock for counter
The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software
PDMA Controller
– Support up to 32 independent DMA channels
– Descriptor or No-Descriptor Transfer mode compatible with previous JZ SOC
– A simple Xburst®
-1 CPU supports smart transfer mode controlled by programmable
firmware
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 224 - 1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– A dedicated bus interface - BIF interconnects with on-chip BCH
– A dedicated bus interface - NIF interconnects with on-chip NEMC or off-chip NEMC.
– An extra INTC IRQ can be bound to one programmable DMA channel
SAR A/D Controller
– 7 Channels
– Resolution: 12-bit
– Integral nonlinearity: ±1 LSB
– Differential nonlinearity: ±0.5 LSB
– Resolution/speed: up to 2Msps
更多信息可参考“JZ4775 Datasheet”