ADALM-PlutoSDR 上手（四）kernel devices tree分析

参考ADI 提供的 linux/arch/arm/boot/dts里面的设备树的include的关系：
zynq-pluto-sdr-revb.dts
–>zynq-pluto-sdr.dtsi
–>zynq.dtsi
–>zynq-7000.dtsi
由上面4个文件组成，单个列一下每个文件，方便以后分析：
zynq-7000.dtsi

/*
 *  Copyright (C) 2011 - 2014 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "xlnx,zynq-7000";

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu0: cpu@0 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <0>;
            clocks = <&clkc 3>;
            clock-latency = <1000>;
            cpu0-supply = <&regulator_vccpint>;
            operating-points = <
                /* kHz    uV */
                666667  1000000
                333334  1000000
            >;
        };

        cpu1: cpu@1 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <1>;
            clocks = <&clkc 3>;
        };
    };

    fpga_full: fpga-full {
        compatible = "fpga-region";
        fpga-mgr = <&devcfg>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
    };

    pmu@f8891000 {
        compatible = "arm,cortex-a9-pmu";
        interrupts = <0 5 4>, <0 6 4>;
        interrupt-parent = <&intc>;
        reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
    };

    regulator_vccpint: fixedregulator {
        compatible = "regulator-fixed";
        regulator-name = "VCCPINT";
        regulator-min-microvolt = <1000000>;
        regulator-max-microvolt = <1000000>;
        regulator-boot-on;
        regulator-always-on;
    };

    amba: amba {
        u-boot,dm-pre-reloc;
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <1>;
        interrupt-parent = <&intc>;
        ranges;

        adc: adc@f8007100 {
            compatible = "xlnx,zynq-xadc-1.00.a";
            reg = <0xf8007100 0x20>;
            interrupts = <0 7 4>;
            interrupt-parent = <&intc>;
            clocks = <&clkc 12>;
        };

        can0: can@e0008000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clocks = <&clkc 19>, <&clkc 36>;
            clock-names = "can_clk", "pclk";
            reg = <0xe0008000 0x1000>;
            interrupts = <0 28 4>;
            interrupt-parent = <&intc>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };

        can1: can@e0009000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clocks = <&clkc 20>, <&clkc 37>;
            clock-names = "can_clk", "pclk";
            reg = <0xe0009000 0x1000>;
            interrupts = <0 51 4>;
            interrupt-parent = <&intc>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };

        gpio0: gpio@e000a000 {
            compatible = "xlnx,zynq-gpio-1.0";
            #gpio-cells = <2>;
            clocks = <&clkc 42>;
            gpio-controller;
            interrupt-controller;
            #interrupt-cells = <2>;
            interrupt-parent = <&intc>;
            interrupts = <0 20 4>;
            reg = <0xe000a000 0x1000>;
        };

        i2c0: i2c@e0004000 {
            compatible = "cdns,i2c-r1p10";
            status = "disabled";
            clocks = <&clkc 38>;
            interrupt-parent = <&intc>;
            interrupts = <0 25 4>;
            reg = <0xe0004000 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        i2c1: i2c@e0005000 {
            compatible = "cdns,i2c-r1p10";
            status = "disabled";
            clocks = <&clkc 39>;
            interrupt-parent = <&intc>;
            interrupts = <0 48 4>;
            reg = <0xe0005000 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        intc: interrupt-controller@f8f01000 {
            compatible = "arm,cortex-a9-gic";
            #interrupt-cells = <3>;
            interrupt-controller;
            reg = <0xF8F01000 0x1000>,
                  <0xF8F00100 0x100>;
        };

        L2: cache-controller@f8f02000 {
            compatible = "arm,pl310-cache";
            reg = <0xF8F02000 0x1000>;
            interrupts = <0 2 4>;
            arm,data-latency = <3 2 2>;
            arm,tag-latency = <2 2 2>;
            cache-unified;
            cache-level = <2>;
        };

        mc: memory-controller@f8006000 {
            compatible = "xlnx,zynq-ddrc-a05";
            reg = <0xf8006000 0x1000>;
        };

        ocmc: ocmc@f800c000 {
            compatible = "xlnx,zynq-ocmc-1.0";
            interrupt-parent = <&intc>;
            interrupts = <0 3 4>;
            reg = <0xf800c000 0x1000>;
        };

        uart0: serial@e0000000 {
            compatible = "xlnx,xuartps", "cdns,uart-r1p8";
            status = "disabled";
            clocks = <&clkc 23>, <&clkc 40>;
            clock-names = "uart_clk", "pclk";
            reg = <0xE0000000 0x1000>;
            interrupts = <0 27 4>;
        };

        uart1: serial@e0001000 {
            compatible = "xlnx,xuartps", "cdns,uart-r1p8";
            status = "disabled";
            clocks = <&clkc 24>, <&clkc 41>;
            clock-names = "uart_clk", "pclk";
            reg = <0xE0001000 0x1000>;
            interrupts = <0 50 4>;
        };

        spi0: spi@e0006000 {
            compatible = "xlnx,zynq-spi-r1p6";
            reg = <0xe0006000 0x1000>;
            status = "disabled";
            interrupt-parent = <&intc>;
            interrupts = <0 26 4>;
            clocks = <&clkc 25>, <&clkc 34>;
            clock-names = "ref_clk", "pclk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

        spi1: spi@e0007000 {
            compatible = "xlnx,zynq-spi-r1p6";
            reg = <0xe0007000 0x1000>;
            status = "disabled";
            interrupt-parent = <&intc>;
            interrupts = <0 49 4>;
            clocks = <&clkc 26>, <&clkc 35>;
            clock-names = "ref_clk", "pclk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

        qspi: spi@e000d000 {
            clock-names = "ref_clk", "pclk";
            clocks = <&clkc 10>, <&clkc 43>;
            compatible = "xlnx,zynq-qspi-1.0";
            status = "disabled";
            interrupt-parent = <&intc>;
            interrupts = <0 19 4>;
            reg = <0xe000d000 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        smcc: memory-controller@e000e000 {
            #address-cells = <1>;
            #size-cells = <1>;
            status = "disabled";
            clock-names = "memclk", "aclk";
            clocks = <&clkc 11>, <&clkc 44>;
            compatible = "arm,pl353-smc-r2p1";
            interrupt-parent = <&intc>;
            interrupts = <0 18 4>;
            ranges ;
            reg = <0xe000e000 0x1000>;
            nand0: flash@e1000000 {
                status = "disabled";
                compatible = "arm,pl353-nand-r2p1";
                reg = <0xe1000000 0x1000000>;
                #address-cells = <0x1>;
                #size-cells = <0x1>;
            };
            nor0: flash@e2000000 {
                status = "disabled";
                compatible = "cfi-flash";
                reg = <0xe2000000 0x2000000>;
                #address-cells = <1>;
                #size-cells = <1>;
            };
        };

        gem0: ethernet@e000b000 {
            compatible = "cdns,zynq-gem", "cdns,gem";
            reg = <0xe000b000 0x1000>;
            status = "disabled";
            interrupts = <0 22 4>;
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            clock-names = "pclk", "hclk", "tx_clk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

        gem1: ethernet@e000c000 {
            compatible = "cdns,zynq-gem", "cdns,gem";
            reg = <0xe000c000 0x1000>;
            status = "disabled";
            interrupts = <0 45 4>;
            clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
            clock-names = "pclk", "hclk", "tx_clk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

        sdhci0: sdhci@e0100000 {
            compatible = "arasan,sdhci-8.9a";
            status = "disabled";
            clock-names = "clk_xin", "clk_ahb";
            clocks = <&clkc 21>, <&clkc 32>;
            interrupt-parent = <&intc>;
            interrupts = <0 24 4>;
            reg = <0xe0100000 0x1000>;
            broken-adma2;
        };

        sdhci1: sdhci@e0101000 {
            compatible = "arasan,sdhci-8.9a";
            status = "disabled";
            clock-names = "clk_xin", "clk_ahb";
            clocks = <&clkc 22>, <&clkc 33>;
            interrupt-parent = <&intc>;
            interrupts = <0 47 4>;
            reg = <0xe0101000 0x1000>;
            broken-adma2;
        };

        slcr: slcr@f8000000 {
            #address-cells = <1>;
            #size-cells = <1>;
            compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
            reg = <0xF8000000 0x1000>;
            ranges;
            clkc: clkc@100 {
                #clock-cells = <1>;
                compatible = "xlnx,ps7-clkc";
                fclk-enable = <0xf>;
                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
                        "gem1_aper", "sdio0_aper", "sdio1_aper",
                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
                        "dbg_trc", "dbg_apb";
                reg = <0x100 0x100>;
            };

            rstc: rstc@200 {
                compatible = "xlnx,zynq-reset";
                reg = <0x200 0x48>;
                #reset-cells = <1>;
                syscon = <&slcr>;
            };

            pinctrl0: pinctrl@700 {
                compatible = "xlnx,pinctrl-zynq";
                reg = <0x700 0x200>;
                syscon = <&slcr>;
            };
        };

        dmac_s: dmac@f8003000 {
            compatible = "arm,pl330", "arm,primecell";
            reg = <0xf8003000 0x1000>;
            interrupt-parent = <&intc>;
            interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
                "dma4", "dma5", "dma6", "dma7";
            interrupts = <0 13 4>,
                         <0 14 4>, <0 15 4>,
                         <0 16 4>, <0 17 4>,
                         <0 40 4>, <0 41 4>,
                         <0 42 4>, <0 43 4>;
            #dma-cells = <1>;
            #dma-channels = <8>;
            #dma-requests = <4>;
            clocks = <&clkc 27>;
            clock-names = "apb_pclk";
        };

        devcfg: devcfg@f8007000 {
            compatible = "xlnx,zynq-devcfg-1.0";
            interrupt-parent = <&intc>;
            interrupts = <0 8 4>;
            reg = <0xf8007000 0x100>;
            clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
            clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
            syscon = <&slcr>;
        };

        efuse: efuse@f800d000 {
            compatible = "xlnx,zynq-efuse";
            reg = <0xf800d000 0x20>;
        };

        global_timer: timer@f8f00200 {
            compatible = "arm,cortex-a9-global-timer";
            reg = <0xf8f00200 0x20>;
            interrupts = <1 11 0x301>;
            interrupt-parent = <&intc>;
            clocks = <&clkc 4>;
        };

        ttc0: timer@f8001000 {
            interrupt-parent = <&intc>;
            interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
            compatible = "cdns,ttc";
            clocks = <&clkc 6>;
            reg = <0xF8001000 0x1000>;
        };

        ttc1: timer@f8002000 {
            interrupt-parent = <&intc>;
            interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
            compatible = "cdns,ttc";
            clocks = <&clkc 6>;
            reg = <0xF8002000 0x1000>;
        };

        scutimer: timer@f8f00600 {
            interrupt-parent = <&intc>;
            interrupts = <1 13 0x301>;
            compatible = "arm,cortex-a9-twd-timer";
            reg = <0xf8f00600 0x20>;
            clocks = <&clkc 4>;
        };

        usb0: usb@e0002000 {
            compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
            status = "disabled";
            clocks = <&clkc 28>;
            interrupt-parent = <&intc>;
            interrupts = <0 21 4>;
            reg = <0xe0002000 0x1000>;
            phy_type = "ulpi";
        };

        usb1: usb@e0003000 {
            compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
            status = "disabled";
            clocks = <&clkc 29>;
            interrupt-parent = <&intc>;
            interrupts = <0 44 4>;
            reg = <0xe0003000 0x1000>;
            phy_type = "ulpi";
        };

        watchdog0: watchdog@f8005000 {
            clocks = <&clkc 45>;
            compatible = "cdns,wdt-r1p2";
            interrupt-parent = <&intc>;
            interrupts = <0 9 1>;
            reg = <0xf8005000 0x1000>;
            timeout-sec = <10>;
        };
    };
};

zynq.dtsi

/include/ "zynq-7000.dtsi"

/ {
    interrupt-parent = <&intc>;

    aliases: aliases {
        ethernet0 = &gem0;
        serial0 = &uart1;
    };
};

&gem0 {
    status = "okay";
};

&clkc {
    ps-clk-frequency = <33333333>;
};

&usb0 {
    status = "okay";
    dr_mode = "host"; /* This breaks OTG mode */
};

&uart1 {
    status = "okay";
};

&sdhci0 {
    status = "okay";
};

zynq-pluto-sdr.dtsi

/*
 * ZYNQ Pluto SDR (Z7010/AD9363)
 *
 * Copyright (C) 2016 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */
/include/ "zynq.dtsi"

/ {
    model = "Analog Devices PlutoSDR Rev.A (Z7010/AD9363)";
    memory {
        device_type = "memory";
        reg = <0x00000000 0x20000000>;
    };

    chosen {
        linux,stdout-path = "/amba@0/uart@E0001000";
    };

    clocks {
        ad9364_clkin: clock@0 {
            #clock-cells = <0>;
            compatible = "adjustable-clock";
            clock-frequency = <40000000>;
            clock-accuracy = <200000>; /* 200 ppm (ppb) */
            clock-output-names = "ad9364_ext_refclk";
        };
    };

    usb_phy0: phy0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };

};

&sdhci0 {
    status = "disabled";
};

&watchdog0 {
    status = "okay";
    reset-on-timeout;
};

&usb0 {
    xlnx,phy-reset-gpio = <&gpio0 52 0>;
    dr_mode = "otg";
    status = "okay";
    usb-phy = <&usb_phy0>;
};

&qspi {
    status = "okay";
    is-dual = <0>;
    num-cs = <1>;
    primary_flash: ps7-qspi@0 {
        #address-cells = <1>;
        #size-cells = <1>;
        spi-tx-bus-width = <1>;
        spi-rx-bus-width = <4>;
        compatible = "n25q256a", "n25q512a", "jedec,spi-nor"; /* same as S25FL256 */
        reg = <0x0>;
        spi-max-frequency = <50000000>;
        partition@qspi-fsbl-uboot {
            label = "qspi-fsbl-uboot";
            reg = <0x0 0x100000>; /* 1M */
        };
        partition@qspi-uboot-env {
            label = "qspi-uboot-env";
            reg = <0x100000 0x20000>; /* 128k */
        };
        partition@qspi-nvmfs {
            label = "qspi-nvmfs";
            reg = <0x120000 0xE0000>; /* 1M */
        };
        partition@qspi-linux {
            label = "qspi-linux";
            reg = <0x200000 0x1E00000>; /* 30M */
        };
    };
};

&adc {
    xlnx,channels {
        #address-cells = <1>;
        #size-cells = <0>;
        channel@0 {
            reg = <0>;
        };
    };
};

/ {
    fpga_axi: fpga-axi@0 {
        compatible = "simple-bus";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges;

        axi_i2c0: i2c@41600000 {
            compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
            reg = <0x41600000 0x10000>;
            interrupt-parent = <&intc>;
            interrupts = <0 59 4>;
            clocks = <&clkc 15>;
            clock-names = "pclk";

            #address-cells = <1>;
            #size-cells = <0>;

        };

        rx_dma: dma@7c400000 {
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x7c400000 0x10000>;
            #dma-cells = <1>;
            interrupts = <0 57 0>;
            clocks = <&clkc 16>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <2>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <0>;
                    adi,length-width = <24>;
                };
            };
        };

        tx_dma: dma@7c420000 {
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x7c420000 0x10000>;
            #dma-cells = <1>;
            interrupts = <0 56 0>;
            clocks = <&clkc 16>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <0>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <2>;
                    adi,length-width = <24>;
                    adi,cyclic;
                };
            };
        };

        cf_ad9364_adc_core_0: cf-ad9361-lpc@79020000 {
            compatible = "adi,axi-ad9361-6.00.a";
            reg = <0x79020000 0x6000>;
            dmas = <&rx_dma 0>;
            dma-names = "rx";
            spibus-connected = <&adc0_ad9364>;
            adi,axi-decimation-core-available;
        };

        cf_ad9364_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {
            compatible = "adi,axi-ad9364-dds-6.00.a";
            reg = <0x79024000 0x1000>;
            clocks = <&adc0_ad9364 13>;
            clock-names = "sampl_clk";
            dmas = <&tx_dma 0>;
            dma-names = "tx";
            adi,axi-interpolation-core-available;
            adi,axi-dds-default-scale = <0>;
        };

        mwipcore@43c00000 {
            compatible = "mathworks,mwipcore-axi4lite-v1.00";
            reg = <0x43c00000 0xffff>;
        };
    };
};

&spi0 {
    status = "okay";

    adc0_ad9364: ad9361-phy@0 {
        #address-cells = <1>;
        #size-cells = <0>;
        #clock-cells = <1>;
        compatible = "adi,ad9363a";

        /* SPI Setup */
        reg = <0>;
        spi-cpha;
        spi-max-frequency = <10000000>;

        /* Clocks */
        clocks = <&ad9364_clkin 0>;
        clock-names = "ad9364_ext_refclk";
        clock-output-names = "rx_sampl_clk", "tx_sampl_clk";

        /* Digital Interface Control */

         /* adi,digital-interface-tune-skip-mode:
          * 0 = TUNE RX&TX
          * 1 = SKIP TX
          * 2 = SKIP ALL
          */
        //adi,digital-interface-tune-skip-mode = <0>;

        adi,pp-tx-swap-enable;
        adi,pp-rx-swap-enable;
        adi,rx-frame-pulse-mode-enable;

        adi,xo-disable-use-ext-refclk-enable;

        /* Enable CMOS Mode */
        adi,full-port-enable;
        adi,digital-interface-tune-fir-disable;

        /* Temporary workaround - HDL issue? need to investigate further */
        adi,digital-interface-tune-skip-mode = <0>; /* SKIP TX */
        adi,tx-fb-clock-delay = <0>;
        adi,tx-data-delay = <9>;
        adi,swap-ports-enable;

        /* Mode Setup */

        //adi,split-gain-table-mode-enable;

        /* ENSM Mode */
        adi,frequency-division-duplex-mode-enable;
        //adi,ensm-enable-pin-pulse-mode-enable;
        //adi,ensm-enable-txnrx-control-enable;


        /* adi,rx-rf-port-input-select:
         * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
         * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
         * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
         *
         * 3 = RX1A_N and RX2A_N enabled; unbalanced
         * 4 = RX1A_P and RX2A_P enabled; unbalanced
         * 5 = RX1B_N and RX2B_N enabled; unbalanced
         * 6 = RX1B_P and RX2B_P enabled; unbalanced
         * 7 = RX1C_N and RX2C_N enabled; unbalanced
         * 8 = RX1C_P and RX2C_P enabled; unbalanced
         */

        adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
        adi,rx-rf-port-input-select-lock-enable;

        /* adi,tx-rf-port-input-select:
         * 0    TX1A, TX2A
         * 1    TX1B, TX2B
         */

        adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
        adi,tx-rf-port-input-select-lock-enable;

        //adi,update-tx-gain-in-alert-enable;
        adi,tx-attenuation-mdB = <10000>;

        adi,rf-rx-bandwidth-hz = <18000000>;
        adi,rf-tx-bandwidth-hz = <18000000>;
        adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
        adi,tx-synthesizer-frequency-hz = /bits/ 64 <2450000000>;

        /*              BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
        adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
        /*              BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
        adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>;

        /* Gain Control */

        /* adi,gc-rx[1|2]-mode:
         * 0 = RF_GAIN_MGC
         * 1 = RF_GAIN_FASTATTACK_AGC
         * 2 = RF_GAIN_SLOWATTACK_AGC
         * 3 = RF_GAIN_HYBRID_AGC
         */

        adi,gc-rx1-mode = <2>;
        adi,gc-rx2-mode = <2>;
        adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
        adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
        adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
        adi,gc-lmt-overload-high-thresh = <800>; /* mV */
        adi,gc-lmt-overload-low-thresh = <704>; /* mV */
        adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
        adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
        //adi,gc-dig-gain-enable;
        //adi,gc-max-dig-gain = <15>;

        /* Manual Gain Control Setup */

        //adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
        //adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
        adi,mgc-inc-gain-step = <2>;
        adi,mgc-dec-gain-step = <2>;

        /* adi,mgc-split-table-ctrl-inp-gain-mode:
         * (relevant if adi,split-gain-table-mode-enable is set)
         * 0 = AGC determine this
         * 1 = only in LPF
         * 2 = only in LMT
         */

        adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

        /* Automatic Gain Control Setup */

        adi,agc-attack-delay-extra-margin-us= <1>; /* us */
        adi,agc-outer-thresh-high = <5>; /* -dBFS */
        adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
        adi,agc-inner-thresh-high = <10>; /* -dBFS */
        adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
        adi,agc-inner-thresh-low = <12>; /* -dBFS */
        adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
        adi,agc-outer-thresh-low = <18>; /* -dBFS */
        adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

        adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
        adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
        adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
        //adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
        adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
        adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
        adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
        //adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
        //adi,agc-dig-gain-step-size = <4>; /* 1..8 */

        //adi,agc-sync-for-gain-counter-enable;
        adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
        //adi,agc-immed-gain-change-if-large-adc-overload-enable;
        //adi,agc-immed-gain-change-if-large-lmt-overload-enable;

        /* Fast AGC */

        adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
                //adi,fagc-allow-agc-gain-increase-enable;
                adi,fagc-lp-thresh-increment-steps = <1>;
                adi,fagc-lp-thresh-increment-time = <5>;

                adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
                adi,fagc-final-overrange-count = <3>;
                //adi,fagc-gain-increase-after-gain-lock-enable;
                adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
                adi,fagc-lmt-final-settling-steps = <1>;
                adi,fagc-lock-level = <10>;
                adi,fagc-lock-level-gain-increase-upper-limit = <5>;
                adi,fagc-lock-level-lmt-gain-increase-enable;

                adi,fagc-lpf-final-settling-steps = <1>;
                adi,fagc-optimized-gain-offset = <5>;
                adi,fagc-power-measurement-duration-in-state5 = <64>;
                adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
                adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
                adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
                adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
                adi,fagc-rst-gla-large-adc-overload-enable;
                adi,fagc-rst-gla-large-lmt-overload-enable;
                adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
                adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
                adi,fagc-state-wait-time-ns = <260>;
                adi,fagc-use-last-lock-level-for-set-gain-enable;

        /* RSSI */

        /* adi,rssi-restart-mode:
         * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
         * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
         * 2 = ENTERS_RX_MODE,
         * 3 = GAIN_CHANGE_OCCURS,
         * 4 = SPI_WRITE_TO_REGISTER,
         * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
         */
        adi,rssi-restart-mode = <3>;
        //adi,rssi-unit-is-rx-samples-enable;
        adi,rssi-delay = <1>; /* 1us */
        adi,rssi-wait = <1>; /* 1us */
        adi,rssi-duration = <1000>; /* 1ms */

        /* Control Outputs */
        adi,ctrl-outs-index = <0>;
        adi,ctrl-outs-enable-mask = <0xFF>;

        /* AuxADC Temp Sense Control */

        adi,temp-sense-measurement-interval-ms = <1000>;
        adi,temp-sense-offset-signed = <0xCE>;
        adi,temp-sense-periodic-measurement-enable;

        /* AuxDAC Control */

        adi,aux-dac-manual-mode-enable;

        adi,aux-dac1-default-value-mV = <0>;
        //adi,aux-dac1-active-in-rx-enable;
        //adi,aux-dac1-active-in-tx-enable;
        //adi,aux-dac1-active-in-alert-enable;
        adi,aux-dac1-rx-delay-us = <0>;
        adi,aux-dac1-tx-delay-us = <0>;

        adi,aux-dac2-default-value-mV = <0>;
        //adi,aux-dac2-active-in-rx-enable;
        //adi,aux-dac2-active-in-tx-enable;
        //adi,aux-dac2-active-in-alert-enable;
        adi,aux-dac2-rx-delay-us = <0>;
        adi,aux-dac2-tx-delay-us = <0>;

        /* Control GPIOs */

        en_agc-gpios = <&gpio0 66 0>;
        reset-gpios = <&gpio0 67 0>;

    };
};

zynq-pluto-sdr-revb.dts

/dts-v1/;
/include/ "zynq-pluto-sdr.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

&axi_i2c0 {
    current_limiter@5a {
        compatible = "adi,adm1177";
        reg = <0x5a>;
        adi,r-sense-mohm = <50>; /* 50 mOhm */
        adi,shutdown-threshold-ma = <1059>; /* 1.059 A */
        adi,vrange-high-enable;
    };
};

/ {
    model = "Analog Devices PlutoSDR Rev.B (Z7010/AD9363)";

    leds {
        compatible = "gpio-leds";
        led0 {
            label = "led0:green";
            gpios = <&gpio0 15 0>;
            linux,default-trigger = "heartbeat";
        };
    };

    gpio_keys {
        compatible = "gpio-keys";
        #address-cells = <1>;
        #size-cells = <0>;

        button {
            interrupt-parent = <&gpio0>;
            interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
            label = "Button";
            linux,code = <BTN_MISC>;
        };

    };
};