ZYNQ 使用DMA的HP总线读取数据

一，vivado搭建和sdk验证

1，axi4接口，每次从0发送到1023，verilog代码如下

  reg [31:0]S_AXIS_tdata;
  reg  S_AXIS_tlast;
  reg S_AXIS_tvalid; 
  wire FCLK_CLK0;
  wire s_axis_aclk;
  wire s_axis_aresetn;
  wire [3:0]S_AXIS_tkeep;
  wire S_AXIS_tready;
  wire [0:0]gpio_rtl_tri_o;
  wire [0:0]peripheral_aresetn;
  reg [1:0] state;
assign S_AXIS_tkeep = 4'b1111;  
assign s_axis_aclk =  FCLK_CLK0;
assign s_axis_aresetn = peripheral_aresetn;
reg [31:0]S_AXIS_count;


always@(posedge FCLK_CLK0)
begin
     if(!peripheral_aresetn) 
     begin //系统复位
         S_AXIS_tvalid <= 1'b0;
         S_AXIS_tdata <= 32'd0;
         S_AXIS_tlast <= 1'b0;
         S_AXIS_count<=32'b0;
         state <=0;
     end
     else begin
        case(state) //状态机
          0: begin
              if(gpio_rtl_tri_o && S_AXIS_tready) 
             // if(S_AXIS_tready && fifo_int ) 
              begin //当FIFO非满的时候
                        S_AXIS_tvalid <= 1'b1;//设置写FIFO数据有效标志为1
                        S_AXIS_tdata <= fifo_32bit_rd_data;
                        state <= 1;//转入状态1
              end
              else 
              begin
                 S_AXIS_tvalid <= 1'b0;
                 state <= 0;
              end
            end
          1:begin
               if(S_AXIS_tready) 
               begin //当FIFO非满
                                 S_AXIS_tdata <= S_AXIS_tdata + 1'b1;
                                 S_AXIS_count<= S_AXIS_count+1'b1;
                               if(S_AXIS_count == 16'd1022) 
                               begin //从0-1022一共写入1023个字节
                                  S_AXIS_tlast <= 1'b1;//发送最后一个数据
                                  state <= 2;
                               end
                               else 
                               begin
                                  S_AXIS_tlast <= 1'b0;
                                  state <= 1;
                               end
               end
               else 
               begin
                          S_AXIS_tdata <= S_AXIS_tdata;                 
                          state <= 1;
               end
            end       
          2:begin
               if(!S_AXIS_tready) 
               begin //如果FIFO满，等待
                               S_AXIS_tvalid <= 1'b1;//发送全部S_AXIS_tdata数据
                               S_AXIS_tlast <= 1'b1;//发送中断
                               S_AXIS_tdata <= S_AXIS_tdata;
                               state <= 2;
               end
               else 
               begin //写入结束
                      S_AXIS_tvalid <= 1'b0;
                      S_AXIS_tlast <= 1'b0;
                      S_AXIS_tdata <= 16'd0;
                      S_AXIS_count<=0;
                      state <= 0;
               end
            end
         default: state <=0;
         endcase
     end              
end

2,sdk验证：

 二，petalinux axi-dma驱动设置