32位无符号数除法器
/*
32位除法器代码
*/
module div32(
input clk,
input rst_n,
input start,
input [31:0] a,
input [31:0] b,
output done,
output [31:0] yshang,
output [31:0] yyushu
);
reg [63:0] temp_a;
reg [63:0] temp_b;
reg [5:0] i;
reg done_r;
//------------------------------------------------
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
i <= 6'd0;
else if(start && i < 6'd33)
i <= i+1'b1;
else
i <= 6'd0;
end
//------------------------------------------------
always@(posedge clk or negedge rst_n)
if(!rst_n)
done_r <= 1'b0;
else if(i == 6'd32)
done_r <= 1'b1;
else if(i == 6'd33)
done_r <= 1'b0;
assign done = done_r;
//------------------------------------------------
always@(posedge clk or negedge rst_n)begin
if(!rst_n) begin
temp_a <= 64'h0;
temp_b <= 64'h0;
end
else if(start) begin
if(i == 6'd0) begin
temp_a = {32'h00000000,a};
temp_b = {b,32'h00000000};
end
else begin
temp_a = temp_a << 1;
if(temp_a >= temp_b)
temp_a = temp_a - temp_b + 1'b1;
else
temp_a = temp_a;
end
end
end
assign yshang = temp_a[31: 0];
assign yyushu = temp_a[63:32];
endmodule
仿真testbench
`timescale 1ns/1ns
module div32_tb;
parameter CLK_PERIOD=20;
reg clk;
reg rst_n;
reg start;
reg [31:0]a;
reg [31:0]b;
initial
begin
clk=1'b0;
forever begin
clk=#(CLK_PERIOD/2) ~clk;
end
end
initial
begin
rst_n=1'b0;
#200 rst_n=1'b1;
#10000 $stop;
end
initial begin
start = 1'b0;
#1000 start = 1'b1;
end
initial begin
a = 32'd0;
#1000 a=32'd1000;
end
initial begin
b = 32'd0;
#1000 b=32'd145;
end
div32 div32_inst(
.clk(clk),
.rst_n(rst_n),
.start(start),
.a(a),
.b(b),
.done(),
.yshang(),
.yyushu()
);
endmodule
当done信号拉高时，表述输出有效，得到的商为6，余数为130