【verilog】十、时钟信号与复位信号

1.常规时钟

1) initial:

parameter clk_period = 10;

reg clk;

initial begin

clk = 1'b0;

forever

#(clk_period / 2) clk = ~clk;

end

 

2) always:

parameter clk_period = 10;

reg clk;

initial

clk = 0;

always #(clk_period / 2) clk = ~clk;

 

2.占空比可调时钟

//占空比:High_time / (High_time + Low_time)

parameter High_time = 5, Low_time = 10;

reg = clk;

always

begin

clk = 1;

# High_time;

clk = 0;

# Low_time;

end

 

3.偏移相位时钟信号

//相位偏移:360 * pshift_time / (High_time + Low_time)

parameter High_time = 5, Low_time = 10, pshift_time = 2;

reg = clk;

always

begin

clk = 1;

# High_time;

clk = 0;

# Low_time;

end

assign #(pshift_time) clk_p = clk;

 

4.固定数目时钟信号

parameter clk_cnt = 50, clk_period = 2;

reg clk;

initial

begin

clk = 0;

repeat(clk_cnt)

#(clk_period / 2) clk = ~clk;

end

 

5.复位信号

1)异步复位

parameter rst_repiod = 100;

reg rst_n;

initial

begin

rst_n = 0;

#rst_repiod;

rst_n = 1;

end

 

2)同步复位

parameter rst_repiod = 100;

reg rst_n;

initial begin

rst_n = 1;

@(posedge clk)

rst_n = 0;

#rst_repiod;

rst_n = 1;

end

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转载自blog.csdn.net/JifengZ9/article/details/106879198