SEC
CPU reset vector code is in ResetVec.asm16 (Yoga C750 Intel TigerLake Insyde Codebase)
;
; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
; Execution starts here upon power-on/platform-reset.
;
ResetHandler:
nop
nop
ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
;
DB 0x0e9
DW -3
; ORG 0x38
TIMES 0x38-($-$$) DB 0
;
SEC entry point is function _ModuleEntryPoint in Flat32.asm
_ModuleEntryPoint PROC NEAR C PUBLIC
;
; Save BIST state in MM0
;
fninit ; clear any pending Floating point exceptions
movd mm0, eax
;
; Save time-stamp counter value
; rdtsc load 64bit time-stamp counter to EDX:EAX
;
rdtsc
movd mm5, edx
movd mm6, eax
;
; Check INIT#
; Trigger warm reset if PCIEBAR register is not in reset/default value state
;
mov eax, 80000060h ;PCIEX_BAR_REG B0:D0:F0:R60
mov dx, 0CF8h
out dx, eax
mov dx, 0CFCh
in eax, dx
cmp eax, 0
jz NotWarmStart
;
; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
;
mov dx, 0CF9h
mov al, 06h
out dx, al
NotWarmStart:
;
; Enter Protected mode.
;
STATUS_CODE (01h) ; BSP_PROTECTED_MODE_START
mov esi, OFFSET GdtDesc
DB 66h
lgdt fword ptr cs:[si]
mov eax, cr0 ; Get control register 0
or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
mov cr0, eax ; Activate protected mode
mov eax, cr4 ; Get control register 4
or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
mov cr4, eax
;
; Now we're in Protected16
; Set up the selectors for protected mode entry
;
mov ax, SYS_DATA_SEL
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Go to Protected32
;
mov esi, offset NemInitLinearAddress
jmp fword ptr cs:[si]
TightLoop:
cli
hlt
jmp TightLoop
_ModuleEntryPoint ENDP