GIC(Generic Interrupt Controller) is a centralized resource that supports and manages interrupts in a system /*通用中断控制器是系统中支持和管理中断的核心资源*/ GIC provides: /*GIC 提供如下功能：*/ 1、Registers for managing interrupt sources, interrupt behavior, and interrupt routing to one or multiple processors /*提供多个寄存器用于管理中断源、中断行为、以及中断分发到一个或多个处理器*/ 2、Support for /*支持一下功能*/ 1]The ARM architecture Security Extensions /*支持ARM 架构安全扩展*/ 2]Enabling, disabling, and generating processor interrupts from hardware (peripheral) interrupt sources /*支持硬件（外设）中断源使能，禁用和生成处理器中断*/ 3]Generating software interrupts /*支持生成软中断*/ 4]Interrupt masking and prioritization /*支持中断屏蔽和优先排序*/ GIC takes the interrupts asserted at the system level and sends appropriate signals to each connected processor. When GIC implements the Security Extensions, it can implement two interrupt requests to a connected processor. The architecture identifies these requests as IRQ and FIQ /*GIC 产生的中断属于系统级的，它并且会向每个连接的处理器发送适当的信号。当GIC实现安全扩展时，它可以对连接的处理器实施两个中断请求。架构把这两种请求定义为 IRQ 和 FIQ*/ 9.1.1 Features The features of GIC are: Supports three interrupt types: Software Generated Interrupt (SGI) //SGI：软件产生的中断 Private Peripheral Interrupt (PPI) //PPI：专用外设中断 Shared Peripheral Interrupt (SPI) //SPI：共享外设中断 Programmable interrupts that enable you to set the: /*对于可编程中断，你可以做如下设置：*/ Security state for an interrupt. //中断的安全状态 Priority level of an interrupt. //中断的优先级 Enabling or disabling of an interrupt. //中断的使能和禁止 Processors that receive an interrupt. //处理器接收的中断 9.1.2 Security Extensions Support The ARM GIC architecture Security Extensions support: /*ARM GIC 架构安全扩展支持：*/ Configuring each interrupt as either Secure or Non-secure /*将每个中断设置为安全或不安全*/ Signaling Secure interrupts to the target processor by using either the IRQ or FIQ exception request /*通过使用 IRQ 或 FIQ 异常请求将信号安全中断发送到目标处理器*/ Handling priority of secure and Non-secure interrupts, which is a unified scheme. /*按照统一的方法处理安全和非安全中断的优先级*/ Optional lockdown of the configuration of some Secure interrupts. /*某些安全中断的配置的可选锁定*/ In an implementation that includes the Security Extensions: /*在包含安全扩展的实现中：*/ System software individually defines each implemented interrupt as either Secure or Nonsecure. /*系统软件将每个实现的中断分别定义为安全或不安全。*/ The behavior of processor accesses to registers in the GIC depends on whether the access is Secure or Nonsecure. /*处理器访问 GIC 中寄存器的行为取决于访问是安全还是非安全*/ When accessing GIC registers: /*当访问 GIC 寄存器时*/ A Non-secure read of a register field that holds state information for a Secure interrupt returns zero. /*保存安全中断状态信息的寄存器字段的非安全读取返回零。*/ GIC ignores any Non-secure write to a register field that holds state information for a secure interrupt. /*GIC 忽略任何非安全向保存安全中断状态信息的寄存器写入字段*/ Non-secure accesses can only read or set information corresponding to Non-secure interrupts. Secure accesses can read or set information corresponding to both Non-secure and Secure interrupts. /*非安全访问只能读取或设置与非安全中断相对应的信息。安全访问可以读取或设置非安全和安全中断相对应的信息*/ A Non-secure interrupt signals an IRQ interrupt request to a target processor. /*非安全中断只能向目标处理器发送 IRQ 中断请求*/ A Secure interrupt can signal either an IRQ or FIQ interrupt request to a target processor. /*安全中断既可向目标处理器发送 IRQ 中断请求也可发送 FIQ 中断请求*/ 9.1.3 Implementation-Specific Configurable Features //实现指定的配置功能 During implementation of GIC, the features that depend on the configuration are: /*在 GIC 实现过程中，不同的设置有不同的功能*/ Exynos 4412 SCP GIC ConfigurationTotal 160 interrupts including Software Generated Interrupts (SGIs), Private Peripheral Interrupts (PPIs) and Shared Peripheral Interrupts (SPIs) are supported. /* Exynos 4412 SCP GIC 配置支持 160 个中断，包括软件产生的中断（SGIs），专用外设中断（PPIs）和共享外设中断（SPIs）*/ For SPI, you can service maximal 32 × 4 = 128 interrupt requests. /*对于 SPI，你可以维护 128 个中断请求*/ 9.1.4 Terminology //专业术语 This section includes: Interrupt states //中断状态 Interrupt types //中断类型 Model for Handling Interrupts //中断处理模型 Processor Security State and Secure and Non-Secure GIC Accesses //处理器安全状态以及安全和非安全的 GIC 访问 Banking //★是指在同一个地址实现多个副本寄存器，即多个寄存器拥有相同的地址 9.1.4.1 Interrupt States //中断状态 The states that apply at the interface between GIC and each of the processor supported in the system are: /*GIC 与系统支持的每个处理器之间的接口应用状态如下：*/ Inactive: An interrupt that is not active or pending. /*Inactive 状态：中断未触发或挂起。*/ Pending: An interrupt from a source to the GIC that is recognized as asserted in hardware or generated by software and is waiting to be serviced by a target processor. /*Pending 状态：外设硬件或者软件产生产生中断事件，并且该中断事件已经通过硬件信号通知到GIC，现在正在等待 GIC 分配给哪个 CPU 进行处理*/ Active: An interrupt from a source to the GIC that has been acknowledged by a processor, and is being serviced but has not completed. /*Active 状态：CPU 已经应答了该中断请求，并且正在处理中但是还没有处理完*/ Active and Pending: A processor that is servicing the interrupt and GIC has a pending interrupt from the same source /* Active and Pending 状态：当一个中断源处于 Active 状态的时候，同一中断源又触发了中断，此时该中断进入 pending 状态*/ 9.1.4.2 Interrupt Types //中断类型 A device that implements this GIC architecture can manage the following types of interrupt: /*实现此 GIC 架构的设备可以管理以下类型的中断*/ Peripheral Interrupt: A signal asserts this interrupt to the GIC. The types of peripheral interrupt that GIC architecture defines are: /*外设中断：信号将这个中断声明 给 GIC。GIC 架构定义的外设中断类型包括以下两种：*/ PPI: This is a peripheral interrupt that is specific to a single processor. /*PPI：这是特定于单个处理器处理的外设中断*/ SPI: This is a peripheral interrupt that the Distributor can route to any combination of processors. /*SPI：这是一个外设中断，并且该中断可以由分配器路由到处理器组中的任何处理器去处理*/ Each peripheral interrupt is either Edge-Triggered or Level-Sensitive: /*每个外设中断都是边沿触发或者电平敏感*/ o Edge-triggered: This is an interrupt that is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until it is cleared by the conditions defined by this specification. /*Edge-triggered：这是检测到中断信号上升沿时产生的中断，然后该中断一直保持到检测该中断被相关条件清理后才结束，否则将一直保持中断状态*/ o Level-sensitive: This is an interrupt that is asserted whenever the interrupt signal level is HIGH, and disserted whenever the level is LOW. /* Level-sensitive：当检测到中断信号为高电平时触发的中断，当为低电平时置位*/ 9.1.4.2.1 Software-Generated Interrupt //软中断 Software generates this interrupt when writing to a specific register in GIC. The system uses SGIs for interprocessor communication. A software interrupt has edge-triggered properties. On a peripheral input, the software triggering of the interrupt is equivalent to the edge transition of the interrupt signal. Model for Handling Interrupts In a multiprocessor implementation, there are two models for handling interrupts: /*当向 GIC 中特定寄存器写内容时将产生软中断。系统利用 SGI 与处理器间通信。软中断具有边沿触发属性。在外设输入中，软中断等同于中断信号的边沿传输。在多处理器中实现对中断的处理有以下两种模型*/ 1-N model: Only one processor handles this interrupt. The system must implement a mechanism to determine which processor handles an interrupt that is programmed to target more than one processor. /*1-N 模型：只有一个处理器处理该中断。系统必须要能够决定究竟使用哪个处理器来处理该中断*/ N-N model: All processors receive the interrupt independently. When a processor acknowledges the interrupt, the interrupt pending state is cleared only for that processor. The interrupt remains pending for the other processors. /*N-N 模型：所有处理器都会单独地接收到中断。当一个处理器确认中断时，该处理器只能清除自身的中断挂起状态。其他处理器仍保持挂起状态*/ 9.1.4.3 Spurious Interrupts //伪中断 /*一类不希望被产生的硬件中断。发生的原因有很多种，如中断线路上电气信号异常，或是中断请求设备本身有问题*/ It is possible that an interrupt that the GIC has signaled to a processor is no longer required. So, when the processor acknowledges the interrupt, GIC returns a special interrupt ID that identifies the interrupt as a spurious interrupt. /*GIC向处理器发送的中断可能不再需要，因此，当处理器确认中断时，GIC 返回一个特殊的中断 ID 来识别为伪中断。*/ This occurs due to: /*产生的原因如下*/ The change in state of the interrupt. /*中断状态改变*/ Software that has re-programmed the GIC to change the processing requirements for the interrupt. /*软件对 GIC 重新编程从而改变了处理器对中断的请求*/ The interrupt that is handling the 1-N model and the other processor has acknowledged the interrupt. /*在 1-N 模型中断中，其他处理器先于该处理器响应了该中断*/ 9.1.4.4 Processor Security State and Secure and Non-Secure GIC Accesses //处理器安全状态以及安全和非安全的GIC访问 A processor that implements the ARM Security Extensions has a security state: /*实现 ARM 安全扩展的处理器具有安全状态*/ Secure or Non-secure: A processor in the Non-secure state can make only Non-secure accesses to a GIC. /*处理器处于非安全状态下只能通过非安全访问 GIC。*/ A processor in the Secure state can make both Secure and Non-secure accesses to a GIC. /*处理器处于安全状态既可以通过安全也可以非安全的方式访问GIC*/ Software that is running in Non-secure state is described as Non-secure software. /*在非安全状态下运行的软件被描述为非安全软件*/ Software that is running in Secure state is described as Secure software. /*在安全状态下运行的软件被描述为安全软件*/ 9.1.4.5 Banking This section includes: Interrupt Banking Register Banking 9.1.4.5.1 Interrupt Banking In a multiprocessor implementation, for PPIs and SGIs, GIC can have multiple interrupts with the same interrupt ID. Such an interrupt is called a banked interrupt and is identified uniquely by the combination of its interrupt ID and its associated CPU interface. /*在多处理器系统中，对于 PPI 和 SGI， GIC 可以有多个中断使用同一个中断号。这样的中断称为 banked interrupt， 该类中断通过中断号和相关联的 CPUinterface 可以唯一标识。*/ 9.1.4.5.2 Register Banking Register banking refers to implementing multiple copies of a register at the same address. This occurs in: /*Register banking 是指在同一个地址实现多个副本寄存器，即多个寄存器拥有相同的地址（例如：R13 在不同模式下寄存器不同，但都叫 R13）*/ Multiprocessor implementation for some registers that are corresponding to banked interrupts /*in a multiprocessor implementation, to provide separate copies for each processor of registers corresponding to banked interrupts 摘自《GIC 2.0》，表述更加妥当*/ /*在多处理器系统中，为 banked interrupt 的相关寄存器在每个处理器上提供一个独立的 copy。*/ GIC that implements the Security Extensions to provide separate secure and Non-secure copies of some registers. /*在 GIC 实现安全扩展中，提供寄存器的安全与非安全的副本*/ 9.3.1 Functional Interfaces The main blocks of the GIC are: //GIC 主要包括以下主要模块 AMBA slave interface //AMBA 从属接口（关于 AMBA 参见《AMBA 总线规范》） Distributor //分配器 CPU interface //CPU 接口 Clock and reset //时钟和重置 Enable and match signals //使能和匹配信号 9.3.1.1 AMBA Slave Interfaces The AMBA slave interfaces provide access to the GIC registers that enable you to program the system configuration parameters and obtain status information. /*The AMBA slave interfaces 提供对 GIC 寄存器的访问通道，通过该通道可以能够对系统配置参数进行编程同时可以获取状态信息。*/ GIC provides two AMBA slave interfaces: One for the Distributor and one that the CPU interfaces share. /*GIC 提供两个 AMBA slave interfaces：一个用于 Distributor，另一个用于 CPU 接口共享*/ AXI slave interface //参见《AMBA® AXI and ACE Protocol》 Both the AXI slave interfaces use a 32-bit data bus. /*AXI 从属接口都使用32位数据总线*/ The AXI slave interfaces include AXI channels, which are: Write-Address (AW) Write-Data (W) Write-response (B) //写响应 Read-Address (AR) Read-Data (R) 9.3.1.2 Distributor Distributor receives interrupts and provides the highest priority interrupt to the corresponding CPU interface. An interrupt with a lower priority is forwarded to the appropriate CPU Interfaces when it becomes the highest priority pending interrupt. /*Distributor 用于接收中断并向相应的CPU接口提供更高优先级的中断。当一个优先级较低的中断变成最高优先级待处理的中断时，将转发给相应的 CPU 接口*/ 9.3.1.3 CPU Interface A CPU interface contains a programmable interrupt priority mask. /*一个 CPU 接口包含了一个可编程中断优先级的掩码。*/ CPU interface accepts pending interrupts only if the priority of the interrupt is higher than the: /*只有当中断的优先级比下面的高时，CPU interface 才回接收该挂起的中断*/ Programmed interrupt priority mask. //可编程中断优先级的掩码 Interrupts that the processor is currently servicing. //当前处理器正在服务的中断 9.3.1.4 Clock and Reset 9.3.2 The Distributor The Distributor centralizes all interrupt sources and determines the priority of each interrupt. For each CPU interface, the Distributor dispatches the interrupt with the highest priority to the interface for priority masking and preemption handling. /*Distributor 集中所有中断源并且会为每个中断设置一个优先级。对于每个 CPU interface，分配器会将具有最高优先级的中断分派给接口，以实现优先级屏蔽和抢占处理。*/ The Distributor provides a programming interface for: /*Distributor 会为下面提供一个可编程接口*/ Enabling the forwarding of interrupts to the CPU interfaces globally. /*使能全局中断转发到CPU接口*/ Enabling or disabling each interrupt. /*使能和禁止中断*/ Setting the priority level of each interrupt. /*设置中断的优先级*/ Setting the target processor list of each interrupt. /*设置中断的目标处理器*/ Setting each peripheral interrupt to be level-sensitive or edge-triggered. /*设置外设中断是电平敏感还是边沿触发*/ Setting each interrupt as either secure or Non-secure if the GIC implements the Security Extensions. /*GIC 为安全扩展时，设置中断为安全或者非安全的*/ Sending an SGI to one or more target processors. /*将 SGI 中断发送给一个或多个目标处理器*/ The Distributor also provides: Visibility of the state of each interrupt. /*中断状态是否可见*/ A mechanism for software to set or clear the pending state of a peripheral interrupt. /*利用软件设置或清除外设中断挂起状态的机制*/ 9.3.2.1 Interrupt IDs Interrupts from sources are identified using ID numbers. Each CPU interface can see up to 1020 interrupts. The distributor supports up to 1244 interrupts because of banking of SPIs and PPIs. /*中断源内的每个中断都使用中断 ID 进行唯一标识。每个CPU接口最多可以看到1020个中断。由于 SPI 和 PPI 分区原因，Distributor 最多支持1244个中断*/ GIC assigns interrupt ID numbers ID0-ID1019 as follows: /*GIC 如下将中断 ID 号码分配从 ID0-ID1019*/ Interrupt numbers ID32-ID1019 are used for SPIs. /*中断号 32-1019 给 SPI 使用*/ Interrupt numbers ID0-ID31 are used for interrupts that are private to a CPU interface and are banked in the Distributor, in a banked interrupt, the Distributor can have multiple interrupts with the same ID. You can identify a banked interrupt uniquely by its ID number and its associated CPU interface number. The bank interrupt IDs that are used for SGIs and PPIs, respectively are: /*中断号 ID0-ID31 用于 CPU 接口专用的中断，并在 Distributor 中保存。在一个 banked interrupt 中，Distributor 可以让多个中断使用同一个 ID，如果想区分这些 banked interrupt 我们可以通过中断号以及其相关联的 CPUinterface 来唯一标识，banked interrupt 只能用于 SGI 和 PPI，SGI 的 ID 为 0-15，PPI 为 16-31.*/ ID0-ID15 ID16-ID31 In a multiprocessor system: //在多处理器系统中 o A PPI is signaled to a particular CPU interface, and is private to that interface. While prioritizing interrupts for a CPU interface, the distributor considers only the PPIs that are signaled to that interface. /*PPI 是通过信号发送到特定的 CPU 接口，并且该接口是专用的。虽然处理器优先处理 CPU 接口的中断，但 Distributor 所要做的就是将 PPI 的信号发送给对应的 CPUinterface*/ o Each connected processor issues an SGI by writing to the ICDSGIR in the Distributor. Refer to the Software Generated Interrupt Register (ICDSGIR). Each SGI can target multiple processors. In the distributor and in a targeted processor, an SGI is identified uniquely by the combination of its interrupt number, ID0-ID15, and the processor source ID, CPUID0-CPUID7, of the processor that issued the SGI. Banking SGIs refers to the GIC that can handle multiple software interrupts simultaneously without resource conflicts. The Distributor ignores any write to the ICDSGIR that is not from a processor that is connected to one of the CPU interfaces. /*每个连接的处理器通过向 Distributor 中的 ICDSGIR 寄存器写入值来发布 SGI。请参考 ICDSGIR 寄存器。每个 SGI 可以对应多个处理器。在 Distributor 和目标处理器中，SGI 可由中断 ID（0-15） 和发出 SGI 的源处理器 ID（CPUID0-7）来唯一标识。Banking SGI 指的是可以同时处理多个软中断而无资源冲突的 GIC。Distributor 只会对 CPUinterface 中的 ICDSGIR 寄存器进行写操作，如果不是 CPUinterface 中的处理器，那么 Distributor 会忽略写操作。*/ The system software sets the priority of each interrupt independent of its interrupt number. /*系统软件设置每个中断的优先级，与中断号无关*/ 9.3.3 CPU Interfaces Each CPU interface block provides: Interface for a processor that operates with the GIC. /*提供处理器与 GIC 交互的接口*/ Programming interface for: /*可编程接口*/ Enabling the signaling of interrupt requests by the CPU interface. /*通过 CPU 接口使能中断请求信号*/ Acknowledging an interrupt. /*确认中断*/ Indicating completion of the processing of an interrupt. /*确认中断的处理完成*/ Setting an interrupt priority mask for the processor. /*为处理器设置中断优先级掩码*/ Defining the preemption policy for the processor. /*定义处理器的抢占策略*/ Determining the highest priority pending interrupt for the processor. /*确定处理器的最高优先级挂起中断*/ When enabled, a CPU interface takes the highest priority pending interrupt for its connected processor. CPU interface determines whether the interrupt has sufficient priority for it to signal the interrupt request to the processor. /*当使能 CPU 接口时，CPU 接口会为其连接的处理器提供最高优先级挂起中断。 CPU 接口决定中断是否具有足够的优先级，以便将中断请求通知给处理器*/ To determine whether to signal the interrupt request to the processor, the CPU interface considers the interrupt priority mask and the preemption settings for the processor. At any time, the connected processor can read the priority of its highest priority active interrupt from a CPU interface register. /*为了确定是否将中断请求发送给处理器，CPU interface 会综合考虑处理器的中断优先级掩码和抢占设置。在任何时候，连接的处理器都可以从CPU接口寄存器读取其最高优先级活动中断的优先级*/ The processor acknowledges the interrupt request by reading the CPU interface Interrupt Acknowledge Register. The CPU interface returns one of these: /*处理器通过读取CPU接口中断确认寄存器来确认中断请求。CPU接口返回其中之一*/ The ID number of the highest priority pending interrupt. The CPU returns this ID number if that interrupt is of sufficient priority to generate an interrupt exception on the processor. This is the normal response to an interrupt acknowledgement. /*最高优先级挂起中断的 ID。如果该中断的优先级足以在处理器上产生中断异常，则CPU将返回该 ID 号。这是对中断确认的正常响应*/ Exceptionally, an ID number that indicates a spurious interrupt. /*除此之外，将返回一个伪中断的 ID*/ When the processor acknowledges the interrupt at the CPU interface, the Distributor changes the status of the interrupt from pending to either active, or active and pending. Now, the CPU interface can signal another interrupt to the processor to preempt interrupts that are active on the processor. /*当处理器在 CPU接口 处确认中断时，Distributor 将会把该中断状态从挂起状态更改为 active 状态或者 active and pending 状态。现在，CPU 接口可以向处理器发出另一个中断以抢占处理器上处于 active 状态的中断。*/ When there is no pending interrupt with sufficient priority for signaling to the processor, the interface disserts the interrupt request signal to the processor. /*当没有更高优先级的挂起中断要向处理器发送信号时，接口将会把中断请求信号发送给处理器。*/ When the interrupt handler on the processor has completed the processing of an interrupt, it writes to the CPU interface to indicate interrupt completion. Hence, the distributor changes the status of the interrupt either: /*当处理器上的中断处理程序完成中断处理时，它将写入 CPU 接口以表示中断完成。然后 Distributor 就会将中断状态做如下转换*/ From active to inactive or /*active 态变成 inactive 态或者 active and pending 态变成 pending 态*/ From active and pending to pending. /**/ 9.4 Interrupt Handling and Prioritization This section includes: About interrupt handling and prioritization /*关于中断处理和优先级*/ General handling of interrupts /*一般中断处理方式*/ Interrupt prioritization /*中断优先级*/ The effect of the Security Extensions on interrupt handling /*安全扩展对中断处理的影响*/ The effect of the Security Extensions on interrupt prioritization /*安全扩展对中断优先级的影响*/ 9.4.1 About Interrupt Handling and Prioritization Interrupt handling describes: How GIC recognizes interrupts. /*GIC 如何识别中断*/ How software programs GIC to configure and control interrupts. /*如何通过软件编程方式来让 GIC 设置和控制中断*/ How GIC maintains the state machine for each interrupt on each CPU interface. /*GIC 如何维护好 CPU interface 上的每个中断所对应的状态机*/ How the exception model of processor interacts with GIC. /*处理器的异常模式如何与 GIC 交互。*/ Prioritization describes: The configuration and control of interrupt priority. /*中断优先级的设置和控制*/ The order of execution of pending interrupts. /*pending interrupt 的执行顺序*/ The determination of when interrupts are visible to target processor, which includes: /*确定何时中断对目标处理器可见*/ Interrupt priority masking. /*中断优先级的掩码*/ Interrupt grouping. /*中断分组*/ Preemption of an active interrupt. /*抢占已激活的中断*/ 9.4.1.1 Handling Different Interrupt Types in a Multiprocessor System //在多处理器系统中处理不同的中断类型 GIC supports peripheral interrupts and SGIs. /*GIC 支持外设中断和软中断*/ In a multiprocessor implementation, the GIC handles: SGIs that use an N-N model. Peripheral (Hardware) interrupts that use a 1-N model. /*在多处理器实现过程中，GIC 的处理方式是 SGI 使用 N-N 模式，外设中断使用 1-N 模式*/ 9.4.1.2 Identifying the Supported Interrupts //识别支持的中断 GIC defines different ID values for the different types of interrupt. However, there is no requirement for GIC to implement a continuous block of interrupt IDs for any interrupt type. /*GIC 为不同类型的中断定义不同的 ID 值。然而并没有要求 GIC 为每个中断类型都实现一个连续的中断 ID 区域*/ To handle interrupts efficiently, software should know what interrupt IDs are supported by the GIC. Software can use ICDISERs to discover this information. /*为了有效处理中断，软件应该要知道 GIC 支持哪些中断 ID。软件可以利用 ICDISER 寄存器来知道该中断 ID 是否为 GIC 所支持的，并且是否使能*/ When the processor implements the Security Extensions, Secure software determines which interrupts are visible to Non-secure software. The Non-secure software should know which interrupts it can see, and might use this discovery process to find this information. /*当处理器实现安全扩展时，安全软件将决定哪些中断对非安全软件可见。非安全软件应该知道它可以看到哪些中断，并可能使用此发现过程来查找此信息。*/ ICDISER0 provides the Set-enables bits for: SGIs: SGIs use interrupt IDs 15-0 that correspond to register bits[15:0]. PPIs: PPIs use interrupt IDs 31-16 that correspond to register bits[31:16]. /*ICDISER0 寄存器为下面的 SGI 和 PPI 提供设置使能位： SGI：ICDISER0 寄存器的[15:0]位用于 SGI（中断号15-0）的使能设置 PPI：ICDISER0 寄存器的[31:16]位用于 PPI（中断号31-16）的使能设置*/ The remaining ICDISERs, from ICDISER1, provide the Set-enable bits for the SPIs, starting at interrupt ID 32. Software identifies those interrupts that are supported: /*剩下的从 ICDISER1 开始用户 SPI 的使能设置，中断号从32开始。软件会识别下面的那些是 GIC 支持的中断*/ 1. Read the ICDICTR. Refer to Interrupt Controller Type Register (ICDICTR). The ITLinesNumber field identifies the number of implemented ICDISERs, and therefore the maximum number of SPIs that might be supported. /*读取 ICDICTR 寄存器。具体参见 ICDICTR 寄存器。该寄存器的 ITLinesNumber[4:0] 位标识实施 ICDISER 寄存器的数量，同样也可标识所能支持的 SPI 的最大数量*/ 2. Write 0 to the ICDDCR. Enable bit to disable forwarding of interrupts to CPU interfaces. Refer to Distributor Control Register for more information. /*向 ICDDCR 寄存器写 0。使能位禁止将中断转发到 CPU 接口。想了解更多信息请参阅 Distributor Control Register(ICDDCR)*/ 3. For each implemented ICDISER that start with ICDISER0: Write 0xFFFFFFFF to the ICDISER. Read the value of the ICDISER. Bits that read as 1 correspond to supported interrupt IDs. /*每个实施 ICDISER 寄存器都是从 ICDISER0 开始： 向 ICDISER 寄存器写入 0xFFFFFFFF 读取 ICDISER 的值。值为 1 的位就是对应于所支持的中断 ID*/ Software uses the ICDICERs to discover which interrupts are enabled permanently. Refer to Interrupt ClearEnable Registers (ICDICERn) for more information. It does this discovery as follows. For each implemented ICDICER, starting with ICDICER0: /*软件使用 ICDICER 寄存器来知道哪些中断是永久使能的。具体请参加 ICDICERn 寄存器。通过该寄存器我们能获得如下信息。对于每个 implemented ICDICER，都是从 ICDICER0 开始的*/ Write 0xFFFFFFFF to the ICDICER. This disables all interrupts that can be disabled. /*向 ICDICER 寄存器写入 0xFFFFFFFF。表示禁用所有可以禁用的中断*/ Read the value of the ICDICER. Bits that read as 1 correspond to interrupts that are enabled permanently. /*读取 ICDICER 的值。值为 1 的位对应于永久使能的中断*/ Write 1 to any bits in the ICDICER that correspond to interrupts that should be re-enabled. /*将1写入 ICDICER 中需要重新使能的中断所对应的位*/ GIC implements the same number of ICDISERs and ICDICERs. /*GIC 使用相同数量的 ICDISER 和 ICDICER*/ When software has completed its discovery, it writes 1 to the ICDDCR. Enable bit to enable forwarding of interrupts to CPU interfaces. /*当软件完成发现时，它将 1 写入 ICDDCR。使能位会将使能中断转发给 CPU interfaces*/ If GIC implements the Security Extensions, software can use secure accesses to: /*如果GIC 实施安全扩展，软件可以使用安全访问*/ Discover all the supported interrupt IDs. /*发现所有支持的中断 ID*/ Write to the ICDISRs. This is to configure interrupts as secure or Non-secure. Refer to Interrupt Security Registers (ICDISRn). /*如果GIC 实施安全扩展，软件可以使用安全访问去发现所有支持的中断 ID 以及 写 ICDISR 寄存器。这是将中断配置为安全或不安全。详细参见 ICDISR 寄存器。*/ Software that uses the Non-secure accesses can discover only the interrupts that are configured as Non-secure. /*使用非安全访问的软件只能发现配置为不安全的中断。*/ After the software discovers its supported interrupts, when secure software changes the security configuration of any interrupts, it should communicate the effect of those changes to the Non-secure software. /*软件发现其支持的中断之后，当安全软件更改任何中断的安全配置时，它应将这些更改的效果传达给非安全软件*/ 9.4.2 General Handling of Interrupts //中断的一般处理 The Distributor maintains a state machine for each supported interrupt on each CPU interface. The possible states of an interrupt are: Inactive Pending Active Active and pending /*Distributor 为每个CPU接口上的每个受支持的中断维护一个状态机。中断的可能状态有：Inactive、Pending、Active 和 Active and pending。*/ When GIC recognizes an interrupt request, it marks its states as pending. Regenerating a pending interrupt does not affect the state of the interrupt. /*当 GIC 识别到一个中断请求时，它会将该中断的状态标记为挂起。重新产生待处理的中断不会影响中断的状态*/ GIC operates on interrupts as follows: /*GIC 按如下操作中断*/ 1. GIC determines whether each interrupt is enabled. A disabled interrupt has no further effect on GIC. /*1、GIC 确定每个中断是否被使能。禁用的中断对 GIC 没有进一步的影响*/ 2. For each enabled interrupt that is pending, the Distributor determines the targeted processor or processors. /*2、对于每个待处理的使能中断，Distributor 将确定目标处理器为一个还是多个。*/ 3. For each processor, the Distributor determines the highest priority pending interrupt. This is based on the priority information that it holds for each interrupt and forwards the interrupt to the CPU interface. /*3、对于每个处理器，Distributor 决定最高优先级等待中断。这是基于它为每个中断提供的优先级信息，并将中断转发到CPU接口。*/ 4. The CPU interface compares the interrupt priority with the current interrupt priority for the processor. This comparison is determined by a combination of the Priority Mask Register, the current preemption settings, and the highest priority active interrupt for the processor. If the interrupt has sufficient priority, GIC signals an interrupt exception request to the processor. /*4、CPU 接口将处理器的中断优先级与当前中断优先级进行比较。比较的内容由优先级屏蔽寄存器、当前的抢占设置以及处理器的最高优先级活动中断共同决定。如果中断具有足够的优先级，则 GIC 向处理器发出中断异常请求。*/ 5. When the processor takes the interrupt exception, it reads the ICCIAR in its CPU interface to acknowledge the interrupt. Refer to Interrupt Acknowledge Register (ICCIAR). This read returns an Interrupt ID that the processor uses to select the correct interrupt handler. When it recognizes this read, GIC changes the state of the interrupt: /*当处理器接收中断异常时，它会读取 CPU 接口中 ICCIAR 寄存器的值来确认中断。具体参见 ICCIAR 寄存器。读取返回处理器用于选择正确的中断处理程序的中断ID。当处理器识别出这个读取结果时，GIC改变中断的状态：*/ From pending to active and pending if the pending state of the interrupt persists when the interrupt becomes active, or if the interrupt is generated again. /*如果当中断的状态变成 active 或者重新产生了一个中断时，仍然还存在 pending 状态的中断，那么此中断的状态将由 pending 变成 active and pending。*/ Otherwise, GIC changes its state from pending to active. /*否则，GIC 会将其状态由 pending 变成 active。*/ NOTE: 1. A level-sensitive peripheral interrupt persists when it is acknowledged by the processor. This is because the interrupt signal to the GIC remains asserted until the interrupt service routine (ISR) that running on the peripheral is asserting the signal. /*当处理器确认中断时，电平敏感的外设中断仍然存在。这是因为发送到 GIC 的中断信号仍然存在，直到外设上运行的 ISR 清楚信号。*/ 2. In a multiprocessor implementation, the GIC handles: /*在多处理器实现中，GIC 处理方式如下：*/ - SGIs: SGIs use N-N model, where the acknowledgement of an interrupt by one processor has no effect on the state of the interrupt on other CPU interfaces. /*SGI：SGI 使用 N-N 模型，其中一个处理器确认中断对其他 CPU 接口上的中断状态没有影响。*/ - Peripheral interrupts: Peripheral interrupts use 1-N model, where the acknowledgement of an interrupt by one processor removes the pending status of the interrupt on any other targeted processors. /*外设中断：外设中断使用的是 1-N 模型，如果其中一个处理器确认了中断，那么其他其他目标处理器上中断的挂起状态也会被移出*/ 6. When the processor has completed handling the interrupt, it signals this completion by writing to the ICCEOIR in GIC, Refer to End of Interrupt Register (ICCEOIR). /*处理器完成中断处理后，它会通过写入到 GIC 中的 ICCEOIR 寄存器来表示处理完毕，请参见寄存器 ICCEOIR。*/ The GIC requires the order of completion of interrupts by a particular processor to be the reverse of the order of acknowledgement so the last interrupt acknowledged must be the first interrupt completed. /*★ GIC要求指定处理器中断的完成顺序与确认顺序相反，因此最后一个被确认的中断必须是第一个完成的中断。*/ When the processor writes to the ICCEOIR, the GIC changes the state of the interrupt for the corresponding CPU interface, either: /*当处理器写入 ICCEOIR 时，GIC 将更改相应 CPU 接口的中断状态从 active 到 inactive 或者 active and pending 到 pending */ - From active to inactive Or - From active and pending to pending If there is no pending interrupt of sufficient priority for the CPU interface to signal it to the processor, the interface de-asserts the interrupt exception request to the processor. /*如果等待的中断中都没有足够的优先级能让 CPU 接口向处理器发出信号，那么接口将对处理器的中断异常请求解除置位。*/ A CPU interface never signals any interrupt to the connected processor that is active and pending. However, it only signals interrupts that are pending and have sufficient priority: /*CPU接口本身不会向已连接的处理器发送信号告知中断当前处于 active and pending 状态。他只会告知处理器当前中断是 pending 状态以及拥有足够的优先权而已。*/ For SPIs, the interface never signals any interrupt that is active and pending on any CPU interface. /*对于SPI，接口不会向任何一个 CPU 接口上发送信号通知说该中断处于 active and pending 状态。*/ For SGIs, the interface never signals any interrupt that is active and pending on this interface. However, it does not consider whether the interrupt is active and pending on any other interface. /*对于SGI，接口不会向对应的 CPU 接口发送信号通知该中断处于 active and pending 状态。他不会关心在其他接口上该中断是否处于 active and pending 状态*/ Any PPI is private to this interface and the interface does not signal it if it is active and pending. /*每个 PPI 都有对应的专用接口，并且如果该中断处于 active and pending 状态时，则该接口不会向处理器发送信号*/ 9.4.2.1 Interrupt Controls in GIC //GIC 里中断控制器 This sub-section includes: Enabling interrupt //使能中断 Setting and clearing pending state of an interrupt //设置和清除中断的等待状态 Finding the active or pending state of an interrupt //寻找处于 active 或者 pending 状态的中断 Generating an SGI //产生软中断 9.4.2.1.1 Enabling Interrupt For peripheral interrupts, a processor: Enables an interrupt by writing to the appropriate ICDISER bit. Refer to Interrupt Set-Enables Registers (ICDISERn) for more information. Disables an interrupt by writing to the appropriate ICDICER bit. Refer to Interrupt Clear-Enable Registers (ICDICERn) for more information. /*对于外设中断，处理通过向 ICDISER 寄存器的对应位写值来使能或者禁止该中断。具体参加 ICDISER 中断*/ Writes to the ICDISERs and ICDICERs control whether the Distributor forwards interrupts to the CPU interfaces. Disabling an interrupt by writing to the appropriate ICDICER does not prevent that interrupt from changing state, for example, changing state to pending. /*向 ICDISER 和 ICDICER 寄存器的控制器写入是否要 Distributor 中断转发至 CPU 接口。向 ICDICER 寄存器相应位写值能禁用中断，但是不会阻止该中断改变的状态，例如将中断状态改为 pending*/ 9.4.2.1.2 Setting and Clearing Pending State of an Interrupt For peripheral interrupts, a processor: Sets the pending state by writing to the appropriate ICDISPR bit. Refer to Interrupt Set-Pending Registers (ICDISPRn) for more information. Clears the pending state by writing to the appropriate ICDICPR bit. Refer to Interrupt Clear-Pending Registers (ICDICPRn) for more information. /*对于外设中断，处理器通过向 ICDISPR 寄存器相应位写值来设置或清除 pending 状态，详见 ICDISPR 寄存器。*/ For a level-sensitive interrupt: If the hardware signal of an interrupt is asserted when a processor writes to the corresponding ICDICPR bit then the write to the register has no effect on the pending state of the interrupt. If a processor writes a "1" to an ICDISPR bit, then the corresponding interrupt becomes pending regardless of the state of the hardware signal of that interrupt. The interrupt remains pending regardless of the assertion or de-assertion of the signal. /*对于电平敏感的中断： 当处理器对 ICDICPR 寄存器写操作时，如果此时该中断的硬件信号有效，那么寄存器的写操作不会影响中断的 pending 状态。 如果向 ICDISPR 寄存器写1，那么无论中断的硬件信号的状态如何，相应的中断都会被挂起。无论信号是否被确认，中断都会保持等待状态*/ For SGIs, GIC ignores writes to the corresponding ICDISPR and ICDISCR bits. A processor cannot change the state of a SGI by writing to these registers. /*对于 SGI，GIC 会忽略向 ICDISPR 和 ICDISCR 寄存器相应位的写操作。即便向这些寄存器写操作处理器也不会改变 SGI 的中断状态。*/ 9.4.2.1.3 Finding the Active or Pending State of an Interrupt A processor can find: The pending state of an interrupt by reading the corresponding ICDISPR or ICDICPR bit. The active state of an interrupt by reading the corresponding ICDABR bit. Refer to Active Bit Registers (ICDABRn) for more information. /*处理器能够通过读取 ICDISPR 或 ICDICPR 寄存器相应位的值知道中断的状态是 pending 还是 active。详情请参见 ICDABR 寄存器*/ If the interrupt is pending or active, the corresponding register bit is set to 1. If an interrupt is pending and active, the corresponding bit is set to1 in both registers. /*如果中断处于 pending 或者 active 状态时，那么对应的寄存器位会被设置为 1.如果中断处于 pending and active 状态，那么 ICDABR 寄存器和 ICDISPR or ICDICPR 寄存器都会被设置为 1.*/ For an SGI, the corresponding ICDISPR and ICDICPR bits read-as-one (RAO). This happens when there is a pending interrupt from at least one generating processor that targets the processor reading the ICDISPR or ICDICPR. /*★对于 SGI，ICDISPR 和 ICDICPR 寄存器的相应位要设置成 RAO。当至少有一个产生中断处理器产生一个挂起中断时，这时 GIC 里中断控制器就会把读取 ICDISPR 或者 ICDICPR 寄存器值的处理器当成目标。*/ 9.4.2.1.4 Generating an SGI A processor generates an SGI by writing to an ICDSGIR. Refer to Software-Generated Interrupt Register for more information. An SGI can target multiple processors, and the ICDSGIR write specifies the target processor list. The ICDSGIR includes optimization for: Interrupting only the processor that writes to the ICDSGIR Interrupting all processors other than the one that writes to the ICDSGIR. /*当对 ICDSGIR 寄存器写操作时，处理器会产生一个软中断。参加 ICDSGIR 寄存器。一个 SGI 可以定位多个处理器，并且 ICDSGIR 寄存器会记录所有的目标处理器。ICDSGIR 寄存器同时包括对下面情况做最优化处理： 仅中断写入 ICDSGIR 寄存器中的处理器 中断除了 ICDSGIR 寄存器中的处理器以外的处理器*/ SGIs from different processors use the same interrupt IDs. Therefore, any target processor can receive SGIs with the same interrupt ID from different processors. On the CPU interface of the target processor, the pending status of each of these interrupts is independent of the pending status of any other interrupt. However, only one interrupt with this ID can be active. Reading the ICCIAR for an SGI returns both the interrupt ID and the CPU ID of the processor that generated the interrupt, uniquely identifying the interrupt. /*不同处理器所对应的 SGI 使用相同的中断 ID。因此，任何目标处理器都可以接收来自不同处理器的相同中断 ID 的 SGI。在目标处理器的 CPU 接口上，每个中断的挂起状态与任何其他中断的挂起状态无关。但是拥有此 ID 的中断只能有一个处于 active 状态。读取SGI 的 ICCIAR 寄存器将返回产生中断的处理器的中断 ID 和 CPU ID，这样才能唯一标识该软中断*/ In a multiprocessor implementation, the interrupt priority of each SGI interrupt ID is defined independently for each CPU interface, Refer to Interrupt Priority Registers (ICDIPRn). This means that, for each CPU interface, all SGIs with a particular interrupt ID that are pending on that interface have the same priority and must be handled serially. How the CPU interface serializes these SGIs is IMPLEMENTATION DEFINED. /*在多处理器实现中，每个 CPU 接口独立定义各自的 SGI 中断 ID 的中断优先级，参见 ICDIPR 寄存器。这意味着，对于每个 CPU 接口，对于该接口上所有的处于 pending 状态的 SGI （这些 SGI 都有特定的中断 ID）都拥有相同的优先级，这些 SGI 都必须是按照串行处理（依次按照先后顺序处理）。CPU 接口如何串行化这些 SGI 已经定义好了的*/ 9.4.2.2 Implications of the 1-N Model //1-N 模型的实现机制 In a multiprocessor implementation, GIC uses a 1-N model to handle peripheral interrupts that target multiple processors. This means that when GIC recognizes an interrupt acknowledgement from one of the target processors, it clears the pending state of the interrupt on all the other targeted processors. This model means the first available processor can handle this interrupt. However, the interrupt might generate an interrupt exception on multiple targeted processors. For example, two of the targeted processors recognize the interrupt exception request from the GIC at similar times. /*在多处理器实现中，GIC使用 1-N 模型来处理针对多个处理器的外设中断。意思就是当GIC识别来自其中一个目标处理器的中断确认时，它将清除所有其他目标处理器上的中断挂起状态。该模型意思就是第一个使能的处理器会处理该中断。然而，该中断可能会在多个目标处理器上产生中断异常。例如，两个目标处理器可能同时识别来自 GIC 的中断异常请求*/ When multiple target processors attempt to acknowledge the interrupt: A processor reads the ICCIAR and obtains the interrupt ID of the interrupt to be serviced. Refer to Interrupt Acknowledge Register (ICCIAR) for more information. Multiple target processors might have obtained this interrupt ID if the processors read their ICCIARs at very similar times. The system Interrupt Handling and Prioritization Unrestricted Access Non-Confidential requires software on the target processors to ensure that only one processor runs its interrupt service routine. To achieve this, implement a lock on the interrupt service routine (ISR) in shared memory. This operates as follows: Each target processor that obtains the interrupt ID from its read of the ICCIAR runs a semaphore routine. It does this by attempting to obtain a lock on the ISR corresponding to the specified ID value. If a processor fails to obtain the lock, it does no further processing of the interrupt. However, the processor writes the interrupt ID to its ICCEOIR. Refer to End of Interrupt Register (ICCEOIR) for more information. The processor that obtains the lock handles the interrupt and then writes the interrupt ID to its ICCEOIR. /*当多个目标处理器试图确认中断时： 一个处理器读取 ICCIAR 寄存器并获取要提供服务的中断 ID（详情请参加 ICCIAR 寄存器），如果此时其他处理器恰巧也读取了它们的 ICCIAR，那么可能多个目标处理器已经获得了该中断 ID。(处理和优先级无限制非机密访问的)系统中断需要目标处理器上的软件来确保只有一个处理器运行其中断服务程序。为此，会在共享内存中的中断服务程序（ISR）上锁。 操作如下： 每个从 ICCIAR 寄存器中读取并获得中断 ID 的目标处理器都会运行一个信号量程序 它通过尝试获取 ISR 对应的中断 ID 值上的锁来实现此操作 如果处理器无法获得锁，则不会进一步处理该中断，但是，处理器会将中断 ID 写入其 ICCEOIR 寄存器中。参加 ICCEOIR 寄存器 获得锁的处理器处理该中断，同时将将中断 ID 写入其 ICCEOIR 寄存器中*/ A processor reads the ICCIAR and obtains the interrupt ID 1023 by indicating a spurious interrupt. The processor can return from its interrupt service routine without writing to its ICCEOIR. The spurious interrupt ID indicates that the original interrupt is no longer pending. This indication is typically because of another target processor that is handling it. /*处理器读取 ICCIAR 并通过指示伪中断来获得中断ID 1023。处理器可以从其中断服务程序中返回而不用对寄存器 ICCEOIR 写操作。伪中断 ID 表示源中断不再处于等待状态。该指示表示有另外一个处理器正在处理中断。*/ For any processor when an interrupt is active and pending, GIC does not signal an interrupt exception request for this interrupt to any processor until it clears the active status. /*对于任何处理器，当中断处于 active and pending 状态时，并处于等待状态时，GIC不会向处理器发送中断异常请求，直至清除 active 状态为止。*/ NOTE: A GIC implementation t ensures that only one processor can make a 1-N interrupt active by removing the need for a lock on the ISR. This is not required by the architecture, and generic GIC code should not rely on this behaviour. /*注意：GIC实现确保只有一个处理器可以通过移出 ISR 上锁的要求来实现使 1-N 中断处于 active 状态。这不是架构所要求的，通用的 GIC 代码也不应该依赖这种行为。*/ 9.4.2.3 Interrupt Handling State Machine //中断处理状态机 The Distributor maintains a state machine for each supported interrupt on each CPU interface. /*Distributor 为每个 CPU 接口上的每个受支持的中断维护一个状态机*/ When you enable the Distributor and CPU interfaces, the conditions that cause each of the state transitions are as follows: /*当使能 Distributor and CPU interface 时，能够触发每个状态转换的条件如下：*/ Transition A1 or A2, Add Pending Status For an SGI: Transition occurs on a write to an ICDSGIR that specifies the processor as a target. Transition occurs only if the security configuration of the specified SGI, for the appropriate CPU interface, corresponds to the ICDSGIR.SATT bit value. This happens if the GIC implements the Secure Extensions and the write to the ICDSGIR in Secure. /*A1 或 A2 转换过程，添加挂起状态 对于 SGI： 转换发生在向 ICDSGIR 寄存器（指定目标处理器）写操作的时候 只有当适当的CPU接口的指定SGI的安全配置对应于ICDSGIR.SATT位值时才会发生转换，如果 GIC 在 Secure 中实现安全扩展并写入 ICDSGIR，就会发生这种情况*/ For an SPI or PPI, transition occurs if either: A peripheral asserts an interrupt signal or Software writes to an ICDISPR. /*对于 SPI 或者 PPI，转换发生的条件： 外设声明一个中断信号或者软件对 ICDISPR 寄存器写操作*/ Transition B1 or B2, Remove Pending Status Transition not applicable to SGIs: A pending SGI should transition through the active state or reset to remove its pending status. An active and pending SGI should transition through the pending state or reset to remove its pending status. /*B1 或 B2 转换过程，清除挂起状态 转换不适用于 SGI： pending 状态或者 active and pending 状态的 SGI 应该通过 active 状态或者重置来移出 pending 状态来实现转换*/ For an SPI or PPI, transition occurs if either: The level-sensitive interrupt is pending only because of the assertion of an input signal, and that signal is deasserted or The interrupt is pending because of the assertion of an edge-triggered interrupt signal, or a write to an ICDISPR. The software then writes to the corresponding ICDICPR. /*对于 SPI 和 PPI： 电平敏感的中断只有当输入信号被取消才会处于 pending 状态 中断挂起是由于接收到一个边沿触发中断信号或者向 ICDISPR 写操作。软件然后会向相应的 ICDICPR 寄存器写操作*/ Transition C If the interrupt is enabled and of sufficient priority to be signalled to the processor, transition occurs when software reads from the ICCIAR. /*C转换 如果中断使能并且具有足够的优先级来向处理器发送信号，那么当软件从 ICCIAR 寄存器读操作时发生转换*/ Transition D For an SGI, transition occurs if the associated SGI is enabled and the Distributor forwards it to the CPU interface at the same time that the processor reads the ICCIAR to acknowledge a previous instance of the SGI. Whether this transition occurs, depends on the timing of the read of the ICCIAR relative to the reforwarding of the SGI. /*D转换 对于SGI，如果关联的 SGI 被使能并且 Distributor 将其转发到 CPU 接口，同时处理器读取 ICCIAR 值且确认了该中断，此时转换才发生。这种转变是否发生，取决于 ICCIAR 的读取时间与 Distributor 再次转发 SGI 时间是否冲突*/ For an SPI or PPI: Transition occurs when: The interrupt is enabled. Software reads from the ICCIAR. This read adds the active state to the interrupt. Interrupt signal remains asserted for a level-sensitive interrupt. This is because the peripheral does not dissert the interrupt until the processor has serviced the interrupt. /*对于 SPI 和 PPI： 转换发生于： 中断使能 软件读取 ICCIAR 寄存器。读取结果会将 active 状态添加给中断 对于电平敏感的中断，中断信号保持有效。这是因为外设在处理器提供服务中断之前不会将中断取消*/ For an edge-triggered interrupt, whether this transition occurs depends on the timing of the read of the ICCIAR relative to the detection of the reassertion of the interrupt. Otherwise the read of the ICCIAR causes transition C, possibly followed by transition A2. /*对于边沿触发中断，这种转换是否发生取决于ICCIAR的读取相对于检测到中断的重新置位的定时。否则，ICCIAR 的读取会导致转换C，可能会跟随转换 A2*/ Transition E1 or E2, Remove Active Status Transition occurs when software writes to the ICCEOIR. /*E1 和 E2 转换，清除 active 状态 转换发生在软件对 ICCEOIR 寄存器的写操作*/ 9.4.2.4 Special Interrupt Numbers //特殊中断号 The GIC architecture reserves interrupt ID numbers 1020-1023 for special purposes. In a GIC that does not implement the Security Extensions; the only ID number used is ID 1023. This value is returned to a processor, in response to an interrupt acknowledge, if there is no pending interrupt with sufficient priority for it to be signalled to the processor, it is described as a response to a spurious interrupt. /*GIC架构为特殊用途保留中断 ID 号码1020-1023。在不实施安全扩展的GIC中，只能使用 1023.该值会发挥一个处理器，以响应中断确认。如果没有待处理的中断具有足够的优先级以便将其发送给处理器，它被描述为伪中断的响应*/ 9.4.3 Interrupt Prioritization //中断优先权 This sub-section includes: Preemption //抢占 Priority masking //优先权掩码 Priority grouping //优先权组 Software configures interrupt prioritization in GIC by assigning a priority value to each interrupt source. Priority values are 8-bit unsigned binary. A GIC supports a minimum of 16 and a maximum of 256 priority levels. /*软件通过为每个中断源分配一个优先级值来在GIC中配置中断优先级。优先级值为 8 位无符号进制数。GIC支持至少 16 个和最多 256 个优先级。*/ In the GIC prioritization scheme, lower numbers have higher priority. That means, the lower the assigned priority value, the higher is the priority of the interrupt. The highest interrupt priority always has priority field value 0, and the lowest value depends on the number of implemented priority levels as described in Table 9-1 and Table 9-5. /*在GIC 优先级列表中，数字越小，优先级越高。这意味着，分配的优先级值越低，中断的优先级越高。0 的优先级最高。最低值取决于 Table 9-1 and Table 9-5 中实施的优先级数量*/ The ICDIPRs hold the priority value for each supported interrupt. Refer to Interrupt Priority Registers (ICDIPRn) for more information. To determine the number of priority bits implemented, write 0xFF to an ICDIPR priority field and read the stored value. /*ICDIPR为每个支持的中断保存优先级值，请参考 ICDIPR 寄存器。为了确定实现的优先级位数，请将 0xFF 写入 ICDIPR 优先级字段并读取存储的值*/ NOTE: ARM recommends that, before checking the priority range in this way /*注意：ARM 建议在以这种方式检查优先级范围之前*/ 1. For a peripheral interrupt, software first disables the interrupt. /*对于外设中断，软件先禁止中断*/ 2. For an SGI, software first verifies that the interrupt is inactive. /*对于 SGI，软件首先验证中断是否处于 inactive 状态*/ An implementation might reserve an interrupt for a particular purpose and assign a fixed priority to that interrupt. This means that the priority value for that interrupt is read-only. /*一个实现可能会为特定目的保留一个中断，并为该中断分配一个固定的优先级。这意味着该中断的优先级值是只读的*/ This model aligns with the priority grouping mechanism as described in Priority grouping. /*此模型与优先分组中所述的优先分组机制相一致*/ When an interrupt is active on a CPU interface, GIC signals a higher-priority interrupt on that CPU interface, Refer to Preemption section for more information. /*当 CPU 接口上的中断处于 active 状态时，GIC 会在该 CPU 接口上发送一个更高优先级的中断信号，参加 Preemption 部分*/ Software sets the priority of each interrupt in the appropriate ICDIPR. Refer to Interrupt Priority Registers (ICDIPRn) for more information. /*软件在相应的 ICDIPR 寄存器中设置每个中断的优先级。参加 ICDIPR 寄存器*/ 9.4.3.1 Preemption //抢占 A CPU interface supports forwarding of higher priority pending interrupts to a target processor before an active interrupt completes. A pending interrupt is only forwarded if it has a higher priority than all of: /*CPU接口支持在 active 中断完成之前向目标处理器转发更高优先级的 pending 中断，pending 中断只有比以下优先级更高的时候才会被发送：*/ The priority of the highest priority active interrupt on the target processor, the running priority for the processor, Refer to Running Priority Register (ICCRPR). /*目标处理器上最高优先级 active 中断的优先级、处理器的运行优先级，参加 ICCRPR 寄存器*/ The priority mask. Refer to Priority Masking sub-section. /*优先级掩码。参加 Priority Masking sub-section*/ The priority group. Refer to Priority Grouping sub-section. /*优先级组。参加 Priority Grouping sub-section*/ Preemption occurs when the processor acknowledges the new interrupt, and starts to service by preferring to the previously active interrupt or the currently running process. When this occurs, the initial active interrupt is said to have been preempted. /*抢占发生在处理器确认新中断并且正准备服务之前的 active 中断或者当前正在运行的进程的时候。当发生这种情况时，说明初始 active 中断已被抢占*/ Interrupt nesting is sometimes described as starting to service an interrupt while another interrupt is still active. /*中断嵌套有时被描述为在中断仍处于 active 状态时处理器却去为开始为另中断服务*/ 9.4.3.2 Priority Masking ICCPMR for a CPU interface defines a priority threshold for the target processor. Refer Interrupt Priority Mask Register (ICCPMR) for more information. GIC only signals pending interrupts with a higher priority than this threshold value to the target processor. A value of zero, which is the register reset value, masks all interrupts to the associated processor. /*CPU 接口的 ICCPMR 寄存器定义了目标处理器的优先级阈值，参见 ICCPMR 寄存器。只有当 pending 中断的优先级比目标寄存器的优先级阈值高，GIC 才会将信号发送给目标寄存器。如果寄存器的优先级阈值为 0，也就是寄存器复位的值，那么该处理器将屏蔽所有相关的中断。*/ GIC always masks an interrupt that has the largest supported priority field value. This provides an additional means of preventing an interrupt that is being signaled to any processor. /*GIC 总是屏蔽具有最大支持优先级字段值的中断。这提供了一种附加的方式去组织中断被发送给其他寄存器 */ 9.4.3.3 Priority Grouping Priority grouping splits each priority value into two fields: /*优先分组将每个优先级值分成两个字段*/ Group priority //组优先级 Sub-priority //次优先级 GIC uses the group priority field to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt. /*GIC 使用组优先级字段来确定 pending 中断是否具有足够的优先级来抢占当前活动的中断*/ The binary point field in the ICCBPR controls the split of the priority bits into two parts. This 3-bit field specifies how many of the least significant bits of the 8-bit interrupt priority field are excluded from the group priority field. Table 9-6 describes the priority grouping by binary point. /*ICCBPR 寄存器中的二进制点字段控制优先位分为两部分。该 3 位字段指定从组优先级字段中排除的 8 位中断优先级字段的最少有效位数。Table 9-6 通过二进制点位来描述优先级组*/ 9.4.4 The Effect of the Security Extensions on Interrupt Handling //安全扩展对中断处理的影响 If a GIC CPU interface implements the Security Extensions, it provides two interrupt output signals: /*如果 GIC CPU 接口实现安全扩展,它提供了两个中断输出信号*/ IRQ FIQ The CPU interface always uses the IRQ exception request for Non-secure interrupts. Software can configure the CPU interface to use either IRQ or FIQ exception requests for secure interrupts. /*CPU接口始终将 IRQ 异常请求用于非安全中断，软件可以将 CPU 接口配置为使用 IRQ 或 FIQ 异常请求进行安全中断*/ 9.4.4.1 Security Extensions Support //安全扩展支持 Software detects support for the Security Extensions by reading the ICDICTR. SecurityExtn bit Refer to Interrupt Controller Type Register (ICDICTR). /*软件通过读取 ICDICTR 寄存器来检测对安全扩展的支持。SecurityExtn 位请参考 ICDICTR 寄存器*/ Secure software enables secure writes to the ICDISRs to configure each interrupt as Secure or Non-secure. Refer to Interrupt Security Registers (ICDISRn) for more information. /*安全软件可以安全写入 ICDISR，将每个中断配置为安全或不安全。参加 ICDICTR 寄存器*/ In addition: The banking of registers provides independent control of Secure and Non-secure interrupts. The Secure copy of the ICCICR has additional fields to control the processing of Secure and Non-secure interrupts. Refer to CPU Interface Control Register (ICCICR) for more information. /*此外： banking register 提供安全和非安全中断的独立控制。 ICCICR 寄存器的安全副本具有附加字段来控制安全和非安全中断的处理。参见 ICCICR 寄存器*/ These fields are: The SBPR bit: Affects the preemption of Non-secure interrupts. Refer to Control of preemption by Nonsecure interrupts for more information. /*SBPR 位：影响非安全中断的抢占。参见 Control of preemption by Nonsecure interrupts*/ The FIQEn bit: Controls whether the interface signals Secure interrupts to the processor by using the IRQ or FIQ interrupt exception requests. /*FIQEn 位：该位控制接口是否向处理器发送安全中断信号，不管使用IRQ 还是 FIQ 中断异常请求 。*/ The AckCtl bit: Affects the acknowledgment of Non-secure interrupts. Refer to Effect of the Security Extensions on interrupt acknowledgement. /* AckCtl 位：影响非安全中断的确认。参见 Effect of the Security Extensions on interrupt acknowledgement*/ The EnableNS bit: that controls whether Non-secure interrupts are signaled to the processor, and is an alias of the Enable bit in the Non-secure ICCICR. /*EnableNS 位：该位控制接口是否向处理器发送非安全中断信号，同时该位还是非安全 ICCICR 寄存器中的使能位的别名*/ The Non-secure copy of the ICCBPR is aliased as the ICCABPR, Refer to Aliased Binary Point Register (ICCABPR) for more information. This is a secure register, which is only accessible by secure accesses. /*ICCBPR 寄存器的非安全副本是 ICCABPR 寄存器的别名。参加 ICCABPR 寄存器。该寄存器是安全寄存器，它只提供安全通道的访问*/ 9.4.4.2 Special Interrupt Numbers when the Security Extensions are Implemented //安全扩展实施时的特殊中断号 Special interrupt numbers on page 3-11 describes the use of interrupt ID 1023 to indicate a spurious interrupt. The complete list of the interrupt ID numbers that the GIC architecture reserves for special purposes are: /*第 3-11 页中的特殊中断编号描述了使用中断 ID 1023 来表示伪中断。GIC 架构为特殊用途保留的中断 ID 号的完整列表如下：*/ 1020-1021: Reserved. 1022: Used only if GIC implements the Security Extensions //仅在 GIC 实施安全扩展时使用 GIC returns this value to a processor in response to an interrupt acknowledgement only when all of the following apply: /*只有满足以下所有条件时，GIC 才会将此值返回给处理器以响应中断确认：*/ The interrupt acknowledge is a Secure read /*中断确认是安全读取*/ The highest priority pending interrupt is Non-secure /*最高优先级挂起中断是不安全的*/ The AckCtl bit in the Secure ICCICR is set to 0 /*安全 ICCICR 寄存器中的 AckCtl 位设置为0*/ The priority of the interrupt is sufficient for it to be signalled to the processor. /*中断的优先级足以将其发送给处理器*/ 1023: This value is returned to a processor, in response to an interrupt acknowledge, if there is no pending interrupt with sufficient priority for it to be signalled to the processor. /*1023：如果没有挂起的中断具有足够的优先级以便将其通知给处理器，则该值被返回给处理器，以响应中断确认*/ The Secure software treats values of 1022 and 1023 as spurious interrupts on a processor that implements the Security Extensions. /*安全软件将 1022 和 1023 的值视为实现安全扩展的处理器上的伪中断*/ 9.4.4.3 Effect of the Security Extensions on Interrupt Acknowledgement //安全扩展对中断确认的影响 When a processor takes an interrupt, it acknowledges the interrupt by reading the ICCIAR. Refer to General handling of interrupts for more information. A Read of the ICCIAR always acknowledges the highest priority pending interrupt for the processor that performs the read. /*当处理器发生中断时，它通过读 ICCIAR 来确认中断。详情请参见 General handling of interrupts。读 ICCIAR 总是确认读操作的处理器的最高优先级待处理中断*/ If the highest priority pending interrupt is a secure interrupt, the processor must make a secure read of the ICCIAR to acknowledge it. /*如果最高优先级待处理中断是安全中断，则处理器必须对 ICCIAR 进行安全读取以确认它*/ By default, the processor must make a Non-secure read of the ICCIAR to acknowledge a Non-secure interrupt. When the AckCtl bit in the Secure ICCICR is set to "1", the processor can make a secure read of the ICCIAR to acknowledge a Non-secure interrupt. /*默认情况下，处理器必须对 ICCIAR 进行非安全读取以确认非安全中断。当安全 ICCICR 中的 AckCtl 位设置为“1”时，处理器可以安全读取 ICCIAR 以确认非安全中断*/ When the read of the ICCIAR does not match the security of the interrupt by taking into account the AckCtl bit value for a Non-secure interrupt, the ICCIAR read does not acknowledge any interrupt and returns the value: /*当考虑非安全中断的AckCtl位值，ICCIAR的读取结果与中断的安全性不匹配时，ICCIAR 读取不会确认任何中断并返回如下值*/ 1022 for a Secure read when the highest priority interrupt is Non-secure /*当最高优先级中断为非安全时，安全读取1022*/ 1023 for a Non-secure read when the highest priority interrupt is Secure. /*当最高优先级中断为安全时，非安全读取为1023。*/ Refer to Effect of the Security Extensions on reads of the ICCIAR for more information. /*参见 Effect of the Security Extensions on reads of the ICCIAR*/ 9.4.5 The Effect of the Security Extensions on Interrupt Prioritization //安全扩展对中断优先级的影响 When GIC supports the Security Extensions: /*当 GIC 支持安全扩展时*/ Secure software must program the ICDISRs to configure each supported interrupt as either secure or Nonsecure. Refer to Interrupt Security Registers (ICDISRn) for more information. /*安全软件必须对 ICDISR 进行编程，从而为每个支持的中断配置为安全或不安全*/ GIC provides secure and Non-secure views of the interrupt priority settings. /*GIC 提供中断优先级设置的安全和非安全查看*/ The minimum number of supported priority values increases from 16 to 32. /*支持的优先级值的最小数量从 16 增加到 32 */ /*★★GIC 寄存器★★ 1、ICDSGIR(Software Generated Interrupt Register):软中断寄存器（存在于 GIC 的 Distributor 中），通常被用于内部处理器之间的通信 2、ICDISER(Interrupt set-enable register) 3、ICDICTR(Interrupt Controller Type Register)：*/
GIC
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