[M-PHY]Architecture --- PIN, LINE, LANE, SUB-LINK, LINK, and M-PORT

       前言:This section specifies the concept, communication principles, signaling schemes, interface structure and operation of M-PHY interfaces.

       A LANE is a unidirectional, single-signal, physical transmission channel used to transport information from point A to point B. A LANE consists of an M-PHY transmit MODULE (M-TX), an M-PHY receive MODULE (M-RX), and a LINE, which is the point-to-point interconnect between the M-TX and M-RX. An M-TX or M-RX has only one differential electrical output or input LINE interface, respectively, which corresponds with two signaling PINs for each MODULE. The PINs are individually denoted as DP and DN, where DP is defined as the positive node of the differential signal. An optional prefix, TX or RX, can be used to indicate the M-TX or M-RX PINs, respectively. Specifications in this document are defined at the PINs of the M-TX and M-RX, and PINs-to-PINs through the LINE. Figure 1 illustrates the relationship between different parts of an M-PHY LINK.

    
 

一、LINE States

       1、M-PHY technology exploits only differential signaling. a LINE can show the following states:
           (1)A positive differential voltage, driven by the M-TX, which is denoted by LINE state DIF-P
           (2)A negative differential voltage, driven by the M-TX, which is denoted by LINE state DIF-N
           (3)A weak zero differential voltage, maintained by M-RX, which is denoted by LINE state DIF-Z
           (4)An unknown, floating LINE voltage, or no LINE drive, which is denoted by LINE state DIF-Q
       2、Table 1 list all possible LINE conditions with the resulting LINE state:

        

       3、For data transmission, only DIF-P and DIF-N are exploited. DIF-Z can only occur during power-up and power-saving states.

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