In 2000, Verisity Design (now Cadence Design System Inc.) has introduced Verification Advisor (vAdvisor) using the e language, including the incentive to produce automatic alignment strategy, coverage model. e language is an object-oriented language, which is the industry began using object-oriented language to create a test platform.
In 2002, Verisity announced the first library --e reusable verification methodology (eRM).
In 2003, Synopsys announced a reusable library Verification Methodology (RVM), the methodology adopted Synopsys' vera language.
In 2006, Mentor announced a high-level Verification Methodology (AVM). This methodology is mainly using OSCI SystemC transaction level of abstraction methodology (TLM) standard, which is in two languages SystemC and SystemVerilog implementation.
In 2006, Synopsys introduced the Verification Methodology Manual (VMM), this method is RVM from vera SystemVerilog language over to the school.
In 2007, Cadence has introduced a generic reusable Verification Methodology (URM), mainly from the eRM method from E language SystemVerilog over to the school, while adding TLM interfaces, replacing the factory model, configuration mechanism to spur the like.
In 2008, Cadence and Mentor jointly launched the OVM
In 2010, ACCELLERA adopted as the basis for OVM, UVM launched a verification methodology. While introducing some concepts of callbacks VMM. As the industry's unified methodology of a prototype.
2010, Synopsys introduced the VMM1.2, basically follows the TLM communication mechanisms OVM, and using the TLM2.0 (OSCI latest standards), proposed the use of implicit phase OVM and verification process will continue to refine, factories mode replacement mechanism, the establishment of the class hierarchy (parent build relationships). And on this basis, the concept of vmm_timeline to facilitate the realization of a jump between each phase, phase to increase or delete phase. Increased rtl_config concepts. Synopsys company immediately announced the latest version of VCS supports UVM.
From the current perspective on UVM and VMM1.2. No matter what ultimately win, we can see the trend now industry-proven methodology:
1, system modeling, the mainstream industry standard is the use of ESL model with SystemC language, it can be evaluated for its properties. TLM using standard interfaces, SystemC may be seamlessly interfaced to model validation platform, a reference model.
2, for each verification component establishes parent relationship, so that the control is more convenient, conducive environment automatically calls the automatic top phase of the individual components. Establishment of such parent relationship, but also help replace components factory configuration or transaction mode.
3, the establishment of the sub-components of different environment for a certain function (using the UVM agent manner, VMM1.2 employed sub_env manner), each of the sub-components of the environment may be configured to open or close.
4, using the factory mode alternative, at compile time, the environmental configuration, transaction, and other scenes.
5, there is provided API, you can modify the parameters of the environment in the operating phase (the UVM in the base class, VMM1.2 provided by vmm_opts).
6, transaction processor environment, various components, the use of callbacks in the embodiment, the error injection or collection coverage.
7, the register provides an abstraction layer, by way of a script, the automatic generation of a register read and write verification scanning assembly. (VMM provides RAL, will provide the appropriate mechanism UVM later claimed).
8, the process can be controlled environment, such as adding or deleting verification process in the phase, the control jumps between each phase (VMM provides vmm_timeline, will provide the appropriate mechanism after claiming UVM)
Industry-proven methodology trends mentioned above, is 1-5 in Cadence and Mentor, OVM proposed. 6-7 and is set forth in VMM1.1 Synopsys, Inc., whereas 8 VMM1.2 added properties. After VMM1.2 inherits the advantages of the OVM, already it has all of these features, but in The future of UVM UVM proposed increases similar ral and vmm_timeline functions.
Now a comparative perspective UVM and VMM1.2, its advantages and disadvantages mainly in the following areas:
1, UVM is accellra organization launched after verification methodology uniform standards, the main framework for the use of the framework ovm now not out of the official version. Inherits the advantages of the OVM, VMM advantage of inheritance is not enough. And VMM1.2 after inherits the advantages of ovm, and has been improved and strengthened and its function will be temporarily superior to UVM.
2, due to the introduction of new standards is UVM verification methodology, therefore, do not consider the compatibility issues, architecture would be more clear. Source code readability will be relatively strong, and VMM1.2 is necessary to consider the compatibility with VMM1.1, but also consider the new features, and VMM1.1 and VMM1.2 even appear to be two completely different processes, so look messy architecture, code readability is poor.
3, UVM methodology proposed verification platform for more on how to configure, configuration, how should plan how reusable specific methods and ideas in system verification. VMM methodology proposed more module-level verification division verification process in all stages should be doing something wrong injection and so on. These methods and ideas, can be more convenient to use in the library and the VMM library of UVM. Will build verification platform has a good guide.
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