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ODT (On-DieTermination, die termination)
the ODT is DDR1 DDR2 with respect to the key technological breakthroughs, the so-called end (termination), is to make the signal termination circuit is drawn
Closing out without forming the reflection on the circuit, on the back of the impact signal. As the name suggests, ODT termination resistor is to transplant
Into the chip, there is no termination circuit on the motherboard. Entering the era of DDR, DDR memory is more demanding work environment, such as
If the signals previously issued circuit terminal can not be absorbed completely off reflection phenomenon is formed on the circuit, it will affect the signal back
Operation error. So now it supports DDR motherboards are to solve this problem by using the termination resistance. Since each data line at least
A termination resistance, which means that each board requires a lot of DDR termination resistance, which virtually increase the production cost of the motherboard,
And because different memory modules can not be exactly the same as the requirements for termination resistance, but also caused the so-called "memory compatibility issues."
In the DDR-II was added in the ODT function, when operating in the DRAM module to turn off the termination resistor, and for the DRAM die inoperative
Group finalization is performed, play a role in reducing the reflected signal, as shown in Figure 2. ODT function is inhibited by the main control chip,
Be set at boot EMRS, ODT termination signal comprises the DQS, DQS #, DQ, DM like. This can produce
Cleaner signal quality, resulting in a higher memory clock speed. And the termination resistance on the memory chip design can be simplified further
Of the board is designed to reduce the cost of the motherboard, and the termination resistors can be "feature" in line memory chips, thereby reducing the
Appear deposit with the motherboard compatibility issues
Termination schematic diagram of two 0DT
ZQ calibration
As shown in Figure III, DDR3 ZQ is a new pin, on the pin 240 is connected with a low-ohm reference resistor tolerances.
This pin through a set of commands, the automatic correction to the on-chip calibration engine (ODCE, On-DieCalibrationEngine)
Test data output driver is turned on and the termination resistance value of the resistor of ODT. When the system sends this instruction, with the corresponding time
Clock cycle (with 512 clock cycles, after exiting the self refresh operation with 256 clock cycles after power-up and initialization,
) For on-resistance and ODT resistance for recalibration by 64 clock cycles in other cases.
ODT termination is that a resistor to pull the signal lines on your terminal, but the internal resistance with the temperature would
Some subtle changes, in order to ensure that the signal is accurate matching of the terminal, you need a ZQ, ZQ role is to use your outside
Connection, 240R precision resistor for calibration of the internal resistance,
Figure III Reset and ZQ pin
External drive adjustment OCD (Off-ChipDriver)
OCD is a new feature in the DDR-II began to join, but this feature is optional, and some information above is also called offline drive
Adjustment. OCD main role is to adjust the voltage I / O interface terminal, to compensate for the pull-down resistor value, thereby adjusting
Synchronization ensures the integrity and reliability of the signal between the DQS and DQ. During calibration, high were tested DQS and DQ
High, low and a synchronization DQS and DQ where a high level. If not required, by setting the burst length
Of address lines to transmit pull-up / pull-down resistance levels (plus or minus a first gear shift), until it exits tested OCD operation,
To reduce the inclination DQ, DQS OCD operation by the control voltage and to improve the integrity of the signal to improve signal quality.
DETAILED adjustment as shown in Figure 1.
However, in general the stability of the application of environmental requirements are not too high, basically as long as there is a differential DQS
Ensure synchronization accuracy, and adjustment of OCD also have an impact on other operations, so the OCD function in ordinary desktop
And there is no effect on the machine, the advantage is mainly reflected in the very sensitive to the integrity of the data servers and other high-end products.
Figure I OCD
VREFCA & VREFDQ
The memory system is very important for a reference voltage signal VREF, VREF in a DDR3 system is divided into two signals. One for
VREFCA command address signal and services, the other services VREFDQ data bus, it will effectively improve the overall system data
Line signal to noise level, as shown in figure IV.
Figure 4
Reset (Reset)
Reset is DDR3 an important new feature, and specially prepared a pin. This pin DDR3 initialization process will be simplified.
When the Reset command is valid, DDR3 memory will stop all operations, and switch to state a minimum amount of activity, to conserve power. During Reset,
DDR3 memory will be closed most of the functionality inherent, all data received from the transmitter will be closed, and all the internal reset program means,
DLL (delay phase-locked loop) circuit and the clock is stopped, or even ignore any activity on the data bus. As a result, this feature will
So that most DDR3 achieve power saving, as shown in FIG three additional pins.
Data Mask(DM)
Data mask function is also called partial write. Only supports x8 and x16 configuration. DM function TDQS DBI and share the same functional pin. DM function is only used for write operations, and can not be enabled simultaneously with the write DBI function.
It should be said that the highest priority TDQS function, if enabled TDQS then DM and DBI functions are disabled
If the function is disabled TDQS, DM and DBI allowed to play a role. But a little bit I do not understand, DBI and DM does not seem TDQS and Common Pin ah
The data strobe terminal Termination Data Strobe (TDQS)
For x8-DIMMs, each 8 bytes to a selected channel on DQ (DQS / DQS #); for DIMMs x4, the first half
Byte requires a pair of DQ strobe (DQS / DQS #). When mixing two different applications at the same DIMM a system, DQS
The load will be different, this will cause signal integrity issues. TDQS is to solve this problem.
TDQS only for x8 DRAM, but also TDQS together with the use of DM and DM function.
RDIMM0 is x4 DRAM, RDIMM1 a x8 DRAM, RDIMM composed of x4 requires two DQ gate pairs, wherein one pair of connected
X8 received on the RDIMM1 achieve the same function, another for the gate of RDIMM1 is useless, but the connection to the
TDSQ pair, when enabled TDQS, can ensure that all of the same strobe foot load. This ensures the integrity of the signal.
ZQ calibration
There are two commands on the correction ZQ ZQCL (ZQ CALIBRATION LONG) and a ZQ CALIBRATION SHORT (ZQCS)
ZQCL mainly for power system initialization and reset the device, a complete ZQCL requires 512 clock cycles, the subsequent (after initialization and reset), the calibration of a time period to be reduced to 256.
ZQCS tracking continuous voltage and temperature variations during normal operation, ZQCS requires 64 clock cycles.
ZQ calibration sequence
After RESET ZQCL must first clock 512 (tZQINIT) a complete calibration cycle. After ZQCL must tZQOPER (256 clock cycles)
ZQCS command at any time except ATCIVITIES sent,
All BANK must Precharged and time requirements to satisfy tRP
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