On-die Termination (ODT) is a termination matching resistor provided under high-seed in nv-ddr2 interface, which can be enabled optionally.
The general principle is to close when sending cmd and addr, and open when sending or receiving data.
In the flash internal state machine, first determine whether ALE, CLE, DQS, RE_n have level changes.
When ALE, CLE or CE-n jumps from 0->1 rising edge, it means that cmd, addr or chip operation ends, then close ODT.
If it is not amd or addr, then there is a falling edge of DQS 1->0, indicating that it is input data, and the ODT corresponding to DQS and DQ will be turned on;
If it is the falling edge of RE_N 1->0, it means that it is output data, and the DQS and DQ of the flash are the beginning and not the middle terminal, and only the ODT of RE is turned on;
Therefore, under the premise that ODT is enabled by set feature, ODT will be turned on only when DQS and RE have a falling edge change, so the default level of DQS and RE is required to be high.
Because RE# is an active low signal, the default high is fine.
After the DQS signal has sent data, there is a post-amble requirement to keep the low level. It is recommended that DQS==high when idle.