PYNQ development board Vivado PL and PS calls

PYNQ manual schematics pins, etc.
http://www.tul.com.tw/productspynq-z2.html

PL Use

Zynq as an FPGA alone, verilog language

micro USB download, jumpers into JTAG start

In engineering plus boardfile PYNQ of
PYNQ pin constraint

Pressurized source file

code

Light water

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////
 
module PL_LED_TEST(
 input clk,
 input rst,
 output reg [3:0]LED 
);
parameter   CNT_LEN =         4;
reg [25:0] cntr ;
reg [1:0] cnt4 ;
always @ (posedge clk)
    if ( rst ) cntr<=0;
    else if(cntr==49_999_999) 
        cntr<=0;
    else 
        cntr <=cntr+1 ;
always @ (posedge clk)
    if ( rst ) cnt4<=0;
    else if(cntr==49_999_999)
        if(cnt4==3)  
            cnt4<=0;
        else 
            cnt4 <=cnt4+1 ;
                
always @ (posedge clk)
    if ( rst ) LED<=0;
    else if(cnt4==0)           
        LED <=4'b0001;
        else if(cnt4==1)  
            LED <=4'b0010; 
         else if(cnt4==2)  
             LED <=4'b0100;
         else if(cnt4==3)  
             LED <=4'b1000;    
endmodule

build

## This file is a general .xdc for the PYNQ-Z2 board 
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal 50 MHz   20ns

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 4} [get_ports { clk }];


##LEDs

set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0]
set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L6P_T0_34 Sch=led[1]
set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2]
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L23P_T3_35 Sch=led[3]

##Buttons

set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L4P_T0_35 Sch=btn[0]

Generate bit file downloaded to the board

PS

arm as IP core use uart

Plus block design + zynq PS, operation block automation, the preset load pynq
only UART, the other to
generate verilog example
generated bit
introduced sdk