1. Create Zynq's Vivado project
After opening vivado 2018.3, click Create Project to start creating the project:
The first step is an introduction, just click Next to enter the next step:
Set the project name and project saving location. The name can only be English letters, underscores and numbers, and start with a letter. The path of the saved location cannot contain Chinese and other punctuation marks. After setting, click Next:
Keep the default settings and click Next:
Enter the specific chip model in the Search text box (according to the schematic diagram and hardware drawing personnel to determine, sometimes the schematic diagram is not accurately marked), select the chip to be used, and click Next:
Enter the overview of the new project, and click Finish after confirming that it is correct to complete the new project:
2. Create Block Design
2.1 Create Block Design
Click the Block Design of IP INTEGRATOR under the PROJECT MANAGER column, keep the default in the pop-up dialog box, click OK, and enter the Block Design design:
Add the IP core resources required by the project in the Diagram box, perform IP and configuration and port extraction, etc.:
Add the IP core of ZYNQ, click the "+" sign in the middle of the Diagram box, enter zynq in the Search in the pop-up menu, double-click the searched ZYNQ Processing System, complete the IP and addition of the Zynq chip, and the Address Editor appears on the right side of the Diagram Page selection:
2.2 Configuring PS resources
Double-click the IP core of Zynq to enter the Zynq resource settings, and enter the first Zynq resource overview by default, which shows the available resources of Zynq (the green part represents configurable, double-click to enter the corresponding interface):
Select Peripheral I/O Pins to enter peripheral I/O pin configuration (peripheral interface provided by PS):
2.2.1 Peripheral interface configuration
Select the voltage value of Bank 0 and Bank 1. In general design, Bank 0 is LVCMOS 3.3V, Bank 1 is LVCMOS 1.8V, and the Peripheral area is set to the periphery of the PS. Check it directly, and check whether the connection between the interface and the pins of the schematic diagram is correct. Consistent (the number 0~53 on the right side of Peripheral indicates the I/O pin number of PS, and EMIO indicates the I/O pin of PL):
Generally, the settings of PS are relatively common. After checking, you need to check with the schematic diagram. If there is any discrepancy, please check with a hardware drawing colleague.
1. Quad SPI Flash: generally need to be checked, the data interface of the QSPI chip configured for Zynq is used to store the startup file of Zynq, select Single SS 4bit IO (need to be determined according to the specific QSPI manual), and the occupied PS pins Generally use the default;
2. There are two options for Ethernet. Choose according to specific needs. Generally, choose Ethernet 0 (not absolute) for the network port on the front panel of the board. After determining whether the pin is PS or PL according to the schematic diagram, choose Enet0 or EMIO. Expand Afterwards, MDIO also determines whether the pin is PS or PL according to the schematic diagram and chooses MDIO or EMIO;
3. There are two options for USB. In the design, USB0 is basically selected as the USB port (USB1 will conflict with the SD0 pin), which is used to connect to the U disk or card reader:
4. There are two options for SD. In general design, SD0 is the SD card slot, and SD1 is EMMC. If there is an EMMC chip on the board, both SD0 and SD1 need to be checked. No matter whether there is EMMC or not, SD0 must be selected. The common configuration of SD is as follows (check the schematic diagram):
5. There are two types of SPI, which can be selected according to the design needs. It is also necessary to pay attention to whether the position of the pin is PS or PL;
6. There are two UARTs. At present, almost all designs use UART 1 as the serial debugging interface on the front panel, so UART 1 must be checked, and the pins are fixed to use PS 48 and 49:
7. There are two options for I2C, which can be selected according to the design needs. It is also necessary to pay attention to whether the position of the pin is PS or PL;
8. CAN, TTC, SWDT, PJTAG, and TPIU are hardly used in the current design, and will be supplemented later ;
9. Finally, check GPIO MIO and GPIO EMIO, indicating that the remaining PS and PL I/O pins can be used as ordinary GPIO.
After completing the settings of Peripheral I/O Pins above, you can choose MIO Configuration to check the pins, voltage, speed, etc.;
2.2.2 PS-PL Configuration
Select PS-PL Configuration, you can configure the parameters of the interactive interface between PS and PL, configure according to your needs, generally keep the default, sometimes you need to configure the serial port baud rate or configure the HP interface:
2.2.3 Clock configuration
Select Clock Configuration to enter the clock configuration:
Most of the clocks can keep the default settings. Note that the DDR clock may need to be adjusted according to the later system startup. If the system fails to start or reports an error, you may need to try to slow down. Other things that may need to be configured are PL Fabric Clocks, which are determined according to the clocks required by the PL IP cores added later. For example, some of the PL IP cores in this project require 100M clocks, some require 200M clocks, and some require 125M clocks. Others need a 10M clock, which can be set as shown in the figure below. For IP cores that do not require high precision, you can also multiply the frequency of the clock by adding the clock IP to achieve the required clock.
2.2.4 DDR parameter configuration
Select DDR Configuration, set DDR, mainly set the DDR model, according to the schematic diagram and confirm with hardware colleagues, select the correct DDR model, and generally keep the default options for other options:
2.2.5 Interrupt configuration
Select Interrupts, set the interrupt, generally check it as shown in the figure below, for the interrupt of PL network port, PL IIC, etc.:
3.3 Add PL IP core
After the setting is complete, click OK and return to the Diagram. At this time, some new pins will appear in the IP core of ZYNQ:
2.3.1 System reset IP core
Add other IP cores according to the needs of the project. Generally, Processor System Reset is an IP core that must be added. Click the "+" sign to search for "reset" to find:
After adding, you can click Run Block Automation to automatically export the port:
Click Run Connection Automation for automatic connection:
2.3.2 GE network port IP core
Continue to add other IP cores, such as GE network ports of PL (2 GE network ports of PL are added here).
This is just an example. For other types of network ports, refer to the related documents of 
"GE Network Port" .
Run Run Block Automation and Run Connection Automation again (check all):
Automatically add the IP core of AXI DMA, double-click the IP core of AXI 1G/2.5G Ethernet Subsystem, and set the parameters:
Choose 1Gbps, the PHY interface is generally RGMII, SGMII or 1000BaseX, select according to specific needs (the connection of different PHYs may be different, you need to confirm according to the schematic diagram), MAC Features can be kept at default, or you can adjust TX Memory Size and RX Memory Size :
Network Timing and Shared Logic can generally be left as default. If both network ports are RGMII, the Shared Logic of the other network port can be set to "master-slave mode":
Just keep the clock at the default 100K (it seems okay to choose 200K)
Add concat, for connection breaks:
Double-click to set the number of concat ports (set according to the number of interrupts used), here is set to 13 (in addition to the network port, there are other IP cores such as AXI I2C that need to be interrupted):
Manually complete the interrupted connection, doout is connected to IRQ_F2P of ZYNQ, and the In port is connected to the network port and DMA interrupt:
Manually correct the connection of other clocks:
Automatically organize the layout:
For specific settings and connections of other network ports, please refer to High-speed Interface Application and Debugging -GE.docx
2.3.3 AXI IIC IP Core
Add AXI IIC core:
Run Run Connection Automation for automatic connection and manual connection interruption:
It should be noted that the IP core of AXI IIC needs to set the delay. If it is not set, some boards will have " Input/Output error " errors during software operation , which will cause the IIC interface to fail to communicate normally. To add the method, double-click AIX IIC , set as shown in the figure below, the delay experience value is 50 .
2.3.4 Other IP cores
The addition and connection steps of other IP cores are the same as above. AXI Chip2Chip Bridge needs to confirm with FPGA whether to use Aurora, and the two sides must be symmetrical. The IP core of AXI Chip2Chip Bridge is usually configured, and the wUser Width item is automatically generated. FPGA needs to be informed, and Chip2Chip on the FPGA side This one must be consistent with Zynq.
For the specific settings of C2C, please refer to the relevant documents of " C2C Application" in "General Interface" .
2.4 Connection verification
After the project is built, you can verify the connection.
If there is no problem, the following window will pop up, if there is a problem, an error window will pop up, modify the project according to the error message until there is no problem.
2.5 IP core address setting
Set the IP core address in the Address Editor, most of which can be generated by automatic allocation. Among them, the address of Chip2Chip needs to be provided by FPGA (at the same time, you need to pay attention to "Range"), and the address of selectmap is basically unchanged, fixed at 0x43C00000.
3. Project compilation
Generate HDL Wrapper:
Use the default settings, click OK, and wait:
Updating disappears when completed, and Output Products... is generated,
Use the default settings, click OK, and wait for completion:
Comprehensive implementation:
Click OK, there is a green "circle" in the upper right corner:
Complete the implementation and open the design:
Select Layout->I/O Planning in the menu to perform pin constraints, mainly the pin number (consistent with the schematic diagram) and voltage value (usually choose LVCOMS1.8 or LVCOMS3.3, depending on the bank voltage where the pin is located) :
The pin constraints need to correspond to the pins in the schematic diagram. After the constraints are completed, click Save to create an XDC constraint file, enter the XDC file name, and click OK:
Some projects may need to add the following constraints in .xdc, otherwise an error will be reported when compiling the network port:
create_clock -period 8.000 -name ETH0_RGMI_rxc [get_ports ETH0_RGMI_rxc]
Generate a bit file after saving:
Use the default configuration, click OK, and wait for the bit file to be generated. The generated bit file is under impl_1 in the .run directory of the project directory.
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