Vivado sequence detector verilog code ego1 development board verification

Name: vivado sequence detector verilog code ego1 development board verification

Software: VIVADO

Language: Verilog

Code function:

Design a 111 sequence detector.

Requirement: When 3 or more 1's are detected, the output is 1, and in other input cases, the output is 0.

Draw the state transition diagram and complete the Verilog description.

This code has been verified on the ego1 development board. The development board is as follows. Other development boards can modify the pin adaptation:

Code download:vivado sequence detector verilog code ego1 development board verificationName: vivado sequence detector verilog code ego1 development board verification (code Download at the end of the article) Software: VIVADO Language: Verilog code Function: Design a 111 sequence detector. Requirements: When 3 or more 1s are detected, the output is 1, and for other input conditions, the output is 0. Draw a state transition diagram and complete the Verilog description. FPGA code Verilog/VHDL code resource download: www.hdlcode.com This code has been verified on the ego1 development board. The development board is as follows. Other development boards canhttp://www.hdlcode.com/ index.php?m=home&c=View&a=index&aid=319

1. Project documents

2. Program files

3. Program compilation

4. RTL diagram

5. Pin assignment

6. Testbench

7. Simulation diagram

Overall simulation diagram

Frequency division module

Random sequence generation module

State machine control module

Part of the code display:

//Sequence detector, detects the "111" sequence
module sequence_detection(
input clk_in,//clock
input RESET,//Reset
output sequence_led,//Sequence indicator light--D0
output detection_result//Detection result--D3
);
wire random_out;//pseudo-random sequence
wire detection_result_reg;
assign sequence_led=random_out;
wire clk;//1Hz
//
//100M frequency divided to 1Hz
div i_div(
. clk(clk_in),//100M
. clk_out(clk)//1Hz
);
//Pseudo-random sequence generator, used as the detection source of the sequence detector
random_code i_random_code(
.clk(clk),//clock
. RESET(RESET),//reset
.random_out(random_out)//Output pseudo-random signal
    );
//State machine control module
state_ctrl i_state_ctrl(
.clk(clk),//clock
.data_in(random_out),//sequence input
. detection_result_reg(detection_result)//detection result
);
endmodule