Q & A: Filter_ mixer simulation

Q：

Yong Du teacher, hello.

My hand is your "MATLAB and FPGA digital filter to achieve --Altera / Verilog version" of the 2015 first edition.

I am new to this area. In the case of Section 2.4.2 of the mixer ran into problems.

FIG. 2-27 to this step, din is a graph, indicating SinIn.txt read into it.

However s_oc and dout value x, the curve can not be displayed.

 

I use QUARTUS 9.1 web edition. Maybe it is due to version reason, Generate netlist this option is not selected, otherwise this step can not be completed, stagnation.

At compile time, EDA Netlist Writer appear Error, the other did not Error. Tips are "

Error：Can't generate netlist outout files because the file"C：/altera/ XXXXXXXX" is an OpenCore Plus time-limited file.”

In this case, EDA RTL simulation can be run, ModelSim also started. But no output.

Since the release of the reason, TimeQuest Timing Analyser Wizard this step, I was through the completion of "constraint / Create Clock" is complete.

Get a good long time, mainly the above two points may differ and book your step. Finally, only to ask you about, how to deal with? It may be where the problem is.

Thank you.

 

A：

From the message view, it is to break the nuclear issue IP software.

Suggest:

1) The second edition of the book market, the proposed purchase the most recent version of the study.

2) optional package Taobao CRD500 learning development board, development board and fully supporting the book, there is a wealth of information, can improve learning efficiency.

DU Yong