Hello:
I wonder if you excerpt of this part is from there. First, in terms of the IIR filter, the size of the gain G cascaded form, in any case assigned, should not affect the stability of the system, because the stability of the system is determined by the value of the pole of the system, with no G direct relationship; Second, you said data overflow, may refer to an output data range of each filter is input data over the range of the concept for FPGA implementation is concerned, as long as the data range is determined, we can calculate the required data word length, thus here not affect the correctness of the overflow FPGA implementation, that the correct operation can be achieved by adjusting the data word; Third, obviously, save hardware resources into consideration, if G is greater than 1, G will be better allocated to the last one, if G is less than 1, then G is preferably assigned to level 1.
best regard!
DU Yong.
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Subject: Hello teacher
Design teacher, Matlab and FPGA Implementation you write that this digital filter of IIR filter of this section that there is no detail, I would like to ask you to assign this gain G is how to achieve? Thank you, teacher!