Q：
DU teachers Hello, MATLAB and FPGA implementation on digital filter (Altera edition) book section 7.4 of the adaptive equalizer FPGA implementation content, students encounter some problems would like to ask you:
My question is when in practical application (I am now in use PPM modulation communication), AD sampling pulse signal output with a digital signal, our AD using several times the frequency of the signal is better? Before I usually 5 times the sampling, but here I have some questions, if we continue to be sampled five times, then every time the same will be taken to a high level signal to five, and our filter length is 7, 7 is similar with the sampled signals to estimate the intermediate signal. In the case of 5 times that of the sample, 7 which will have five samples from the same high level of output, this is not a good play can not estimate the effect of eliminating ISI ah? Or need longer filter length it?
A：
Your understanding is basically correct. The longer the filter length, balancing the stronger the better, but more resources required logic. Therefore, the design trade-off to consider. Specific balancing effect, you can use MATLAB simulation first, then complete FPGA design.
best regard!
DU Yong
