1. Memory Hierarchy
See more understanding about the locality https://www.jianshu.com/p/fa9aa1db0c0f
Cache and main memory address accessed by the CPU register
CD sequential access disk access in blocks
Pyramid from the bottom up smaller capacity units cost more high-performance access to the faster the better
K-level cache at any time includes a copy of the k + 1 a sub-set of block layer
IDEAL price and capacity close to the lowermost layer, such that the best performance and the
2. The disk gradually increased between DRAM CPU speed gap
DRAM and disk and CPU performance gap is large
Modern computer-based SRAM cache frequently used to try to bridge the gap between the CPU and memory.
This method is effective because the principle of locality.
Memory and external memory 5 orders of magnitude difference
Memory system with the development speed of the CPU fill the gap between the access speed of the CPU and DRAM in full from the CPU closer place.
2004 Multi-core, the effective period of time to be close to the previous rate continued to decline.
Too fast CPU, and disk too slow. They are not able to communicate directly , we can add a layer of excess. This is the role of memory.
In fact, under normal circumstances, read and write speeds faster than disk memory of the tens of thousands of times. So it finally qualify and communicate directly with the CPU.
When the CPU executes the task, only it fetches instructions from memory to communicate with the memory / or write data back to the data. Memory and disk access again, memory read data / instruction from disk or write data back to disk.
TLB set-associative
virtual memory fuuly-associative