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Problem 3
1, the ARM processor operating mode (A) is a protected mode operating system.
A, management mode B, the system mode C, mode user D, external interrupt mode
2, it is known R0 = 0x12345678, R1 = 0x300, then stored in little-endian format, the following statement, R2 = (D)
the STR R0, [Rl]
LDRB R2, [Rl]
A, B 0x12, 0x34
C, 0x56 D, 0x78
3, About the ARM assembler language, the following description is correct (B)
A, ARM assembler language program can be run directly on the ARM microprocessor
B, ARM assembler language typically provides control directives, for controlling the execution of the assembler process
C, the ARM assembler language, can not be defined symbolic constant
operation D, indicated ARM directive statement is done at runtime
4, the following description does not belong to the characteristics of the RISC computer (C)
A, prior to further pipeline per cycle.
B, more general purpose registers.
C, the instruction length is variable, the need to perform a plurality of cycles.
D, independent Load and Store instructions complete the transmission of data between the register and the external memory.
5, the system needs a large amount of data is no longer stored permanently modified, is the most suitable memory (D)
A, B the SRAM, a DRAM
C, D the EEPROM, the Flash
6, the instruction "LDMIA R0!, {R1- R4}" addressing mode is (C)
A, B immediate addressing, register indirect addressing C, D addressed block copy, find the stack
7, following which type is most suitable for embedded processors do FFT (Fast Fourier Transform) calculated (C)
A, B embedded microprocessors, microcontrollers
C, DSP D, above are inappropriate
8, following on von Neumann architecture description is correct (C).
A, program memory space and data memory space separating B, spatially separated storage space IO
C, program memory space and data memory space combined D, IO space combined with storage space
9, ARM7TDMI should begin execution at (A)
A, the ARM state B, Thumb state
C, Specifying an D hardware design by the user, uncertain
10, a description of the exception vector table is correct ARM processor (C)
A, is the exception to the scale discharge interrupt service routine
B, put the exception vector table entry address of the interrupt service routine
C, the exception vector table put the jump instruction, the instruction is executed to enter the corresponding interrupt service routine
D, none of the above
11, the most common data transmission system is an embedded system (B)
A, B query, interrupting C, DMA D, I / O processor
12, the description of the abnormal ARM processor is not correct (C)
A, B Reset exception belongs, division by zero can cause abnormal
C, D all exceptions should return, an external interrupt may cause abnormal
13, the system requires a small amount of cache memory is the most suitable (A)
A, B the SRAM, a DRAM
C, D the EEPROM, the Flash
14, the embedded operating system, typically by (A) means to solve the code size and diversity of the embedded application problems.
A, using customized operating system
B, and the operating system running on multiple processors distributed
C, increase the storage capacity of the embedded device
D, using compression software to compress the operating system
15, soft real-time system requirements (A)
A, in response to events in real-time B, in response to both events and tasks in real-time
C, in response to real-time task D, did not respond to real-time events and tasks
16, depending on real-time basis (A) Real-time interrupt program structure
A, B interrupt response time, maximum execution time of the task
C, D task switching time, the execution time for all other tasks, and
17, belonging to the following ARM instruction is a subroutine call (C)
A, BB, BX C, D BL, MOV
18, the following description of the ARM processor's operating state (D) is not correct.
A, ARM processors have two working conditions.
B, the system is automatically reset after operation state ARM.
C, during program execution, the microprocessor can always switch between the two operating states.
D, must preserve the scene when switching operation.
19, following ARM assembler instruction (B) R1 = R0 × 8 to complete the operation.
A, the ADD Rl, R0, #. 8
B, MULL Rl, R0, #. 8
C, MOV Rl, R0, #. 8
D, MOV Rl, R0, LSL #. 3
20, the following instruction which does not affect the CPSR (A)
A, B CMN, TEQ
C, D SUBS, ADDCS
21,0x27 & 0x15 calculation result is (C)
A, B 0x01, 0x11
C, D 0x05, 0x00
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