Class Exercise 2
1. Which one of the following does not belong to the four levels generally included in the embedded system software structure? (A)
A. Embedded processor
B. Real-time operating system (RTOS)
C. Application programming interface (API) layer
D. Actual application layer
2. An ARM data processing instruction, for example, the immediate number #immed used in "ADD R0, R1, #immed" has certain restrictions. The following immediate number representation is legal (B ).
A.0x00001234
B.0xF000000F
C.0x0000F008
D.0xF080000
3. The μCOS-II operating system does not belong to (C).
A, RTOS
B, preemptive real-time operating system
C, non-preemptive real-time operating system
D, embedded real-time operating system
4. The function of the ARM assembly statement "ADD R0, R2, R3, LSL#1" is (A ).
A. R0 = R2 + (R3 << 1)
B. R0 = (R2<< 1) + R3
C. R3 = R0+ (R2 << 1)
D. (R3 << 1) = R0+ R2
5. The ARM register group has (D) registers.
A, 7 B, 32 C, 6 D, 37
6. Each embedded operating system has its own characteristics to attract relevant users. The following statement is wrong (D).
A. Embedded Linux provides complete network technical support;
B. CLinux is specially developed for ARM chips without MMU;
C. C/OS-Ⅱ operating system is a real-time operating system (RTOS);
D. WinCE provides completely open source code.
7. Store a 32-bit number of four byte units from 0x2168465 to 2000H～2003H. If stored in big-endian mode, the content of the 2000H storage unit is (D).
A, 0x21
B, 0x68
C, 0x65
D, 0x02
8. The following are not the characteristics of embedded systems (C)
A. Embedded systems need special development tools and methods for design.
B. Embedded system is a knowledge integration system that is technology-intensive, capital-intensive, highly decentralized, and constantly innovative.
C. The operating system used by embedded systems is generally not a real-time operating system (RTOS), and the system does not have real-time constraints.
D. Embedded systems are usually task-oriented, and different from general PC computing platforms, they are "dedicated" computer systems
9. In addition to being a general-purpose register, register R15 can also be used as (A)
A. Program counter
B. Link register
C. Stack pointer register
D. Base address register
10. If R1=2000H, (2000H)=0x28, (2008H)=0x87, then execute the instruction LDR R0, [R1, #8]! The value of R0 is (D).
A. 0x2000
B. 0x28
C. 0x2008
D. 0x87
11. The entry address of the FIQ interrupt is (A). (P36)
A, 0x0000001C
B, 0x00000008
C, 0x00000018
D, 0x00000014
12. The ARM instruction set is (B) bit.
A. 16 B. 32 C. 8 D. 24
13. The entry address of the IRQ interrupt is (C).
A, 0x00000000
B, 0x00000008
C, 0x00000018
D, 0x00000014
14. In a real-time operating system, two tasks are executed concurrently. One task waits for a message from its partner or establishes a certain condition before proceeding. This restrictive partnership is called (A).
A. synchronization B. mutual exclusion C. scheduling D. execution
15. ADD R0, R1, #3 belong to (A) addressing mode.
A. Immediate addressing
B. Multi-register addressing
C. Register direct addressing
D. Relative addressing
16. The meaning of the GET directive is (A)
A. Contains an external file
B. Defines the entry of the program
C. Defines a macro
D. Declares a variable
17. Store a 32-bit unit of four bytes from 0x876165 to 2000H to 2003H. If it is stored in little-endian mode, the content of the 2000H storage unit is (C).
A, 0x00 B, 0x87 C, 0x65 D, 0x61
18. Assuming R1=0x31, R2=0x2, after executing the instruction ADD R0, R1, R2 LSL #3, the value of R0 is (C)
A. 0x33,
B. 0x34
C. 0x41
D. 0x39
19. Cache is used to store partial copies of main memory data, and the conversion between the main memory unit address and the Cache unit address is completed with (A).
A. Hardware
B. Software
C. User
D. Programmer
20. The following statement about the storage management unit (MMU) is wrong (B).
A. A key service provided by MMU is to make each task run as a separate program in its own private storage space.
B. Under the control of the operating system with MMU, the running task must know the storage requirements of other unrelated tasks, which simplifies the design of each task.
C. MMU provides some resources to allow the use of virtual memory.
D. MMU acts as a converter to convert the virtual address of the program and data (the link address during compilation) into the actual physical address, that is, the address in the physical main memory.
21. The priority level of IRQ interrupt is (D).
A. 1 B. 2 C. 3 D. 4
22. The addressing mode of LDR R2, [R3,#128] is (C).
A. Register addressing B. Register shift C. Indexed addressing D. Indirect addressing
23. In the following ARM processor modes, (D) mode has its own independent R8-R14 registers. (P31)
A. System mode
B. Termination mode
C. Interrupt mode
D. Fast interrupt mode
24. The difference between NAND FLASH and NOR FLASH is correct. (D)
A. The read speed of NOR is slightly slower than NAND
B. The write speed of NAND is much slower than NOR
C. The erase speed of NAND is much slower than that of NOR
D. Most write operations need to be erased first
25. After the following instructions are executed, the instruction to change the contents of the R1 register is (D).
A, TST R1, #2
B, ORR R1, R1, R1
C, CMP R1, #2
D, EOR R1, R1, R1
3. True or False (2 points for each question, 14 points in total)
1. The ARM processor can handle memory failures in undefined mode and realize virtual memory and memory protection. (F) (P27)
2. In ARM's data processing instructions, most of them can add S after the instruction mnemonic to set the condition code of the status register. (T)
5. The state switching between ARM and Thumb does not affect the mode of the processor or the contents of the register. (T)
6. When the status bit [0] of the operand register Rm is 1, the execution of the BX Rm instruction can enter the Thumb state from the ARM state. (T)
7. The processor core with T variant in the ARM processor structure system can work in ARM state and Thumb state.
(T)