DMA controller of S3C2410
S3C2410 has four channels of DMA controller, each channel has five DMA request sources (that is, five different request methods), including two external request sources connected by pins nXDREQ0 and nXDREQ0, the response signal pin is nXDACK0 and nXDACK0. S3C2410 can also be directly connected to an external DMA controller, the bus request and response signal pins are nXBREQ and nXBACK respectively.
There are three working states of DMA:
DMA working timing:
The DMA of S3C2410 has three basic working modes: single service request mode, single service handshake mode, and full service handshake mode.
Single service request mode:
As long as the DMA request signal is not cancelled, it will continue to lead, and the response signal will continue to respond and transmit data.
Single-service handshake mode:
Each time the DMA request signal is requested, a response is made and a data transfer is performed. That is, if the peripheral needs to transfer data once, it needs to "handshake" with the DMA once, and if it needs to transfer data, it needs to "handshake" again.
Full-service handshake mode: The
DMA request signal requests once, responds once and performs multiple data transfers at intervals. The number of data transfers can be determined according to the set count value.
The sequence diagram is as follows:
The DMA of S3C2410 also has burst mode, which supports continuous reading and writing of four units, which is somewhat different from the full service mode.
The timing diagram is as follows:
The relevant registers of the DMA controller are divided into four categories: configuration registers, initialization registers, status registers, and control registers.
Among them, AHB is the system bus, and APB is the high-speed peripheral bus.