A typical operator of a CPU, a controller, registers and other devices, these devices are connected by an internal bus. Bus in the previous chapter, with respect to the internal CPU bus is external. An internal bus for the connection between the various devices inside the CPU, the external bus for links to other devices on the motherboard and CPU. Simply put, in the CPU:
Operator performs information processing;
Register information storage;
The controller controls the respective devices operate;
An internal bus connected to various devices, for data transmission between them.
For the compilation of a programmer, CPU registers are the main components.
Different CPU, the number of registers, the structure is not the same.
2.1 General Registers
All registers are 16 bits 8086CPU of two bytes can be stored. AX, BX, CX, DX registers four commonly used to store general data is referred to as general purpose registers.
8086CPU previous generation CPU registers are 8-bit, in order to ensure compatibility, so that the original programs written based on the previous generation CPU slightly modified to run on 8086, 8086CPU of AX, BX, CX, DX four registers can be divided into two 8-bit registers can be used independently.
AX can be divided into AH and AL; ....
2.2 word is stored in the register
For reasons of compatibility, 8086CPU can process the data in two dimensions at once.
byte
Word: A word consists of two bytes, two bytes of the word are referred to as upper and lower bytes.
Several assembly instructions 2.3
Write a case-insensitive assembler instruction or the name of a register.
CPU during the execution of this instruction al and ah are two unrelated registers. Do not mistakenly believe that such add al, 93H carry instructions generated are stored in the ah, add al, 93H for 8-bit operation.
If you do add ax, 93H, carry the lower 8 bits are stored in the ah, the CPU 16 that only a register ax when this instruction is executed for the 16-bit operations.
2.4 Physical Address
CPU through the address bus into the memory, must be the physical address of a memory cell. Before issuing the physical address onto the CPU address bus must be formed first physical address internally. Different ways by different CPU can form a physical address. Now we are discussing how to form 8086CPU physical address of the memory unit inside.
2.5 Structure of the CPU 16
The following describes a structure characteristic of one aspect of the CPU:
Operator can handle a maximum of 16-bit data;
The maximum width of the register 16;
Path between registers and 16-bit arithmetic.
Method 2.6 8086CPU given physical address
8086CPU 20 bit address bus, 20-bit address may be transmitted at 1MB addressability. 8086CPU structure 16 is, in the interior of the disposable address processing, transmission 16 is temporarily stored. From the point of view of the internal structure 8086CPU, if the address is simply sent from the inside, then it can only send 16-bit address, showing the addressing capability is only 64KB.
8086CPU use a synthetic approach with the address of two to form a 16-bit 20-bit physical address internally.
When 8086CPU to read and write memory:
The 1.CPU associated components provide two 16-bit addresses, known as a segment address, further referred to as offset addresses
2. The segment offset address into the address and called address adder means through an internal bus; (see the book)
3. The address adder adds two 16-bit address into one 20-bit physical address
4. The address adder 20 through an internal bus address into a physical input-output control circuit
The input and output control circuit 20 to send the physical address of the address bus
6.20 physical address is transferred to the memory address bus
Address adder using physical segment address address = address + offset * 16 synthesized by a physical address and a segment offset address.
We can see: a hexadecimal data left one, multiplied by the equivalent of 16; a decimal data left one, the equivalent multiplied by 10; ....
2.7 "segment address = offset address + 16 * a physical address" essential meaning
No matter how many different logical sense to look at "the segment address * 16 + offset address = physical address" addressing modes, must be well aware of its essential meaning, so as to more flexibly use it to analyze and solve problems . If you just stick the meaning of a certain kind of logic arise out of, and obscure the essence of the meaning of words, the flexible application of such restrictions on the addressing function from consciousness.
The concept of section 2.8
In fact, memory is not segmented, divided segments from the CPU.
Two things to note: * 16 segment address must be a multiple of 16, the starting address of a segment must be a multiple of 16, the offset address is 16-bit, 16-bit addressing capability to address 64KB, so that a segment the maximum length of 64KB.
In 8086PC machine, address storing unit with two elements described, i.e., the address and the segment offset address.
2.9 segment register
When 8086CPU to provide access to memory by the memory unit four segment address segment registers. Look at what this chapter CS
2.10 CS and IP
8086CPU CS and IP are the two most critical registers which indicate the address to read the current CPU instruction. A code segment register CS, IP of the instruction pointer register.
In 8086PC machine, at any time, provided the contents of the CS is M, the content of the IP is N, 8086CPU from memory M * 16 + N unit starts to read and execute an instruction.
The CPU CS: IP points to the content as instruction execution (the difference between instructions and data)
8086CPU working process may be briefly described as follows:
1. From CS: IP to point to the memory cell read command read instruction into the instruction register
2.IP = IP + the length of the instruction is read, thereby pointing to the next instruction; (How do we know the length of this directive is how much?)
3. instruction execution, go to step (1), this process is repeated
After power up or reset 8086CPU (i.e., the CPU start working) and IP are set to the CS CS = FFFFH, IP = 0000H, i.e. when the engine has just started 8086PC, CPU instructions are read from the memory unit FFFF0H performed, FFFF0H the instruction unit is a first instruction to be executed after the power machine 8086PC
2.11 Modify CS, IP instructions
In the CPU, the programmer can be used to read and write the instruction register means only, the programmer control can be achieved by changing the contents of the CPU registers. From where the CPU executes instructions by the CS, the content of the IP determined, the programmer may be controlled by changing the CPU execute the target instruction the CS, IP contents.
mov instruction can not be used to set the value of CS, IP, the reason is very simple, because no 8086CPU provide such functionality, 8086CPU provide further instructions to change their values.
We now introduce a simple can be modified CS, IP of instruction: jmp instruction
To also modify the CS, IP content available "JMP address segment: offset address" instruction is completed.
To edit only the contents of the IP, can be used as form "a legitimate JMP registers" instruction is completed.
2.12 snippet