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Any of a common CPU, such as 8086, are provided with a capability may be performed after completion of execution of instructions currently being executed, is transmitted from the external CPU is detected over a specific message or internally generated, and can immediately receive the the information is processed. This particular information, we can call it: interrupt information.
CPU interrupt information can come from both internal and external
In this chapter, we discuss the internal CPU interrupt information from the
An interrupt is generated in 12.1
Interrupt type code is a byte of data, it may indicate the source of the interrupt 256 kinds of information.
When the internal CPU has the following happens, a corresponding interrupt information.
1: divide error, for example, division of the overflow execution instruction generation div
2: single-step execution
3: instruction execution into
4: int instruction execution
8086CPU interrupted by data type called a code to identify the interrupt source of information.
The above-described four kinds of interrupt sources, 8086CPU type code as follows:
1. divide error: 0
2. Single-step: 1
3. instruction execution into: 4
4. Execute the instruction int, int format of the instruction is n, the number n of the instruction immediately byte is supplied to the CPU interrupt type code.
12.2 interrupt handler
After the CPU receives interrupt information, interrupt information as required for processing. And how information is processed interrupt it can be determined by our programming. In general, the need for different interrupt writing different information processing program.
Seen the first question is, CPU interrupt after receiving the information, how its entrance interrupt handler is determined based on the information.
CPU designers must establish a link between the information and its entry address of the interrupt handler, so that the CPU can find the handler to be executed according to the interrupt information.
The design of the CPU, the interrupt type code is used to effect positioning of the interrupt handler.
Can attendant problem is to locate the interrupt handler, it needs to know the address of the segment and offset addresses, and how to get the interrupt handler segment address and offset address of the terminal based on eight types of code do?
12.3 Interrupt Vector Table
8-bit CPU interrupt by the interrupt type code to find the appropriate entry address of interrupt vector table handler. So what is the interrupt vector it? Or interrupt handler entry address.
Interrupt vector table stored in memory, wherein the stored interrupt sources 256 corresponding to the interrupt handler entry.
In this scheme, a primary issue is how to find CPU interrupt vector table? Now, find the interrupt vector table became interrupt type code found by the interrupt handler entry prerequisite address.
Interrupt vector table stored in memory, for 8086PC machine, designated in memory interrupt vector table address 0. The interrupt vector table storing unit 1024 in 03FF: 0000: 0000-0000.
Then the vector table, an entry in the accounts for how much space it break? Store an entry of an interrupt vector, the interrupt entry address is a handler for 8086CPU, the entry address includes a segment address and offset address, an entry representing the word, high word address segment storage address, low address storing offset address word.
Address memory means for storing N number of interrupt sources corresponding to the offset address of the interrupt handler entry is 4N
Address memory means for storing N number corresponding to the interrupt source of the interrupt handler entry segment address is 4N + 2
12.4 interrupt process
Find the entry address of the ultimate goal is to use it to set the CS and IP, the CPU executes an interrupt handler.
Found with the interrupt vector interrupt type code, and use it to set the CS and IP, this work is done by the CPU hardware automatically.
CPU hardware do this is called the interrupt process.
CPU receives interrupt information to the interrupt process the information, first triggered the interrupt routine. Upon completion of the terminal hardware process, CS: IP will point to interrupt entry handler, CPU starts executing the interrupt handler.
During the interruption, the set CS: IP, you have to save up the original CS and IP values. There when you use a subroutine call instruction calls the same problem, but also to return to the original point of execution to continue after the subroutine, so, call instructions to save the current value of the CS and IP, and then set the CS and IP.
Here is 8086CPU after receiving interruption information, caused by interrupting the process.
1. Get interrupt type code (from interrupt information)
2. The value of the flag stack register (as in the process to change the value of the interrupt flag register, so to save it first in the stack)
3. Set the value of the flag register 0 of 8 and 9 for the TF IF (hereinafter purpose of this step will be described)
4.CS contents of the stack
5.IP contents of the stack
6. From the memory address for the interrupt type code and the interrupt type code * 4 * 4 + 2 word unit reads the entry address of the interrupt handler provided IP and CS.
You can see the CPU save them in the stack. We note that, during the interruption of a job to be done is to set the flags register TF, IF bit, for the purpose of doing so, will be described in the following pages.
Because after executing the interrupt handler, CPU need to restore the site (at a time, the value of each register in the CPU) before entering the interrupt handler. So should register before modifying the logo, it will save the value of the stack.
We interrupt process is described more succinctly, as follows:
1. Get interrupt type code N
2kpushfa
3.TF=0,IF=0
4. push CS
5.push IP
6.IP=N*4 , CS=N*4+2
After the final step, CPU executes interrupt processing program written by the programmer.
12.5 interrupt handler and ire instructions
Since the CPU is detected at any time may interrupt information, that is to say, CPU at any time may execute the interrupt handler, the interrupt handler must always be stored in a certain memory space.
Interrupt handler is quite similar to the preparation methods and routines, the following conventional steps:
1. Save registers used
2. interrupt
3. Restore the registers used
4. iret return instruction.
iret function instruction assembler syntax description is:
pop IP
pop CS
popf
After iret instruction is executed, CPU back to the point before the execution of the interrupt handler continue the program.
12.6 processing division error interrupt
12.7 0 interrupt programming process
We have written a program called do0.
The question now is: Where do0 should put it?
Since we are using a computer on top of the operating system, all hardware resources are under the management of the operating system, so we wanted to get a piece of memory area to store do0, should apply to the operating system.
But here, for two reasons we do not want to do this:
1. apply too much memory will discuss the issue of deviation from the main line
2. We learn a compilation of important aim is to get the bottom of the computer programming experience. So, if possible, we do not care about the operating system, but directly to the hardware resources.
The problem becomes simple and straightforward, we just need to find a memory area other procedures will not be used.
Mentioned front, memory 0000: 0000-0000: 03FF, 1KB size of space to store the system interrupt handler entry address of the vector table. But, in fact, interrupt events systems to process falls far short of 256.
In general, from 0000: 0200-0000: 02FF 256 byte space corresponding to the interrupt vector table are empty.
Conclusion: We can be transferred to the memory do0 0000: 0200.
12.8 Installation
12.9 do0
12.10 set interrupt vector
12.11 Single Step Break
Let's briefly consider how the use of single-step Debug CPU provides interrupt function.
First, Debug interrupt provides a single-step interrupt handler, the function to display the contents of all registers wait for input commands. Then, when the command execution with t, Debug TF is set to 1, so that the CPU operates in single-step interrupt mode.
Before entering the interrupt handler, set TF = 0. Thus avoiding CPU single-step interrupt occurs when executing the interrupt handler.
This is why there is TF = 0 interrupt this step in the process.
(This issue again mull)
Exceptional circumstances in response to interrupts 12.12
In some cases, CPU after the current instruction to complete, even if an interruption occurs, it will not respond. For example: After the instruction for transmitting data to the register ss been performed, even when an interrupt occurs, CPU will not respond.
We should take advantage of this feature, set ss sp and instructions stored in a row, so that the set of instructions provided immediately ss sp instruction execution, and in between this, CPU does not cause an interrupt process.