[UVM] ral test items measured Analysis

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In the module / chip registers to be accessed, it is necessary to use ral model, the test register what it contains?

• Reset values ​​are correct detection register
• Detecting whether a type of the register specified and consistent ralf file (RO / WR / W1C ...)
• If there is adhesion between the bit cross test (detection register of the same register bit different

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Ral model generation

    ralgen -uvm  -l sv  -t  <tb_name>  -o  <ral_model_name>  <ralf_all_file_name>.ralf

     If you need to generate a backdoor Access code needs to add the -b option, if needed income Coverage, you need to add -c baF this option. In the above command, all of a document file RALF <ralf_all_file_name> .ralf file as input, the test configuration is required, the following format:

source ./module_1_name.ralf
source ./moduel_2_name.ralf
 
system ralf_name {
  bytes 4;
  block module_1_name_reg_blk = module_1_name_reg_blk @ 'h25CB0000;
  block module_2_name_reg_blk = module_2_name_reg_blk @ 'h25CC0000;   
}

 

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1. get all the reg ralf

uvm_reg_map    maps[$];
uvm_reg_map    map[$];
uvm_reg        regs[$];
uvm_reg_field  fields[$];
uvm_reg        single_reg;

maps.delete();
model.get_maps(maps);

foreach(maps[j])begin
  maps[j].get_registers(regs);
end

foreach(regs[ii])begin
  regs[ii].get_maps(map);
  regs[ii].get_fields(fields);
end

Detecting the type of register:

 RO: 

1. Get the expected value of preservation field
2. The expected value is written to the field negated
3. check whether the value of change

 RW:

1. Get the expected value of preservation field   
2.  The expected value is written to the field negated
3. Reading this register check whether the change in value
4. Repeat step2-3 

 RC : (This register will be cleared after reading , W0 / W1 no effect)

      1. front door to write all 0 value into this field 

      Front Door to the Read 2.,    the Expect the Read the Back default from the this Field,  proved no effect W0

      3.  Front Door to the Read Again, the Expect the Read the Back All 0 from the this Field,  proven R is cleared (default value premise is not all 0)

      4. front door to write all 1 value into this field   ->   W1

      5. The Front Door to Read , Read Back Expect 0 All        the above demonstrated no effect W1

      The above steps have a question: If the default is 0, then R is unclear whether cleared, it is necessary to go in the back door to write 1

      6. The Back Door All Write to a value INTO the this Field   rear door 1 is written

      7.back door to read all 1 value into       this field to confirm whether the write back door

      8.front door to write all 0 value into this field   W0

      9. Front Door to the Read the Back ,   proved no effect W0 (W1 With the above)

     10. Front Door to the Read Again ,     proof R cleared

 

W1C (write 1 to clear, write 0 has no effect, read no effect)

     1. front door to write all 1

     2. front door to read -> write 1 will prove cleared

    Imperfect above, if the rst value is 0, then no way to judge is to write clear 0 or initial operation is required backdoor

     3. back door to write all 1 value

     4. front door to read all 1

     5.front door to read all 1 value proved no RC

     6.front door to write all 0

     7.front door to read all 1 proved no effect write 0

     8.front door to write all 1

     9.front door to read all 0 1 written proof will be cleared

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bit cross test

      Read and write to the following sequences (using dichotomy check)

      After 8bit 1111_1111_0000_0000 // before the judge can write 8bit will not affect 0/1

      0000_0000_1111_1111

      1111_0000_1111_0000

      0000_1111_0000_1111

      1100_1100_1100_1100

      0011_0011_0011_0011

      1010_1010_1010_1010

      0101_0101_0101_0101

      In this way, for the first 6 bit of the error while writing a 11 bit write verification is less than 0; however, a type of the previous test, have had a full writing ffff and 0000.

 

Detecting whether adjacent register adhesions

         There will be an array of all the reg, Shuffle: adjacent adjacent reg not address the increase randomness

         Order = 1: read and write operations after the completion of a reg, and then operating a write, read and write operation above to see there is no change this value below

         Order = 0: before you get on.