Outline
The use of the watchdog timer resets the microcontroller is within a certain time after entering an error state. When the watchdog is enabled,
If the user program does not "feed the dog" (or reload) within a predetermined period of time, it will produce a watchdog event. Watchdog events
Resulting in a chip reset (if configured to do so).
characteristic
characteristic
If no reload within a programmable timeout period, a reset is generated on-chip;
windowed optional reload operation between a minimum required time-out period and the maximum timeout period occurs, two timeout periods are
It is programmable;
optional alarm interrupt can be generated at the point of time before a programmable watchdog timeout;
programmable prescaler fixed with internal timer 24;
watchdog timeout period may be selected to the desired timing of four times the number of watchdog timer: the 1024 watchdog timer
(T WDCLK × 256 × 4) to over 67 million watchdog clock (T WDCLK × 2 24 × 4);
"safe" watchdog operation. Once the watchdog enable, prohibit claim watchdog reset or hardware reset;
Watchdog oscillator provides a reliable clock source within dedicated chip, the source of the watchdog timer clock is running
Can not be closed;
If the watchdog is enabled, error feed sequence will lead to an immediate watchdog reset;
can choose to protect the watchdog reload value, so that the reload value can only be changed after the "alarm interrupt" time to reach;
signs watchdog reset.
description
4 includes a watchdog fixed prescaler and divide a 24-bit counter. The counter decrements the count clocked
number. Counter starts decreasing the minimum value is 0xFF. If the value is less than 0xFF, 0xFF system will load meter
The number of devices. Thus the minimum watchdog interval (T WDCLK × 256 × 4), the maximum watchdog interval (T WDCLK × 2 24 × 4), both
It is (T WDCLK × 4) multiple. The watchdog should be used according to the following method:
fixed set load value in the watchdog timer WDTC register;
watchdog timer set in the operation mode register WDMOD;
If desired window operation, a register provided in WDWINDOW window watchdog time value;
If an alarm requires interrupt, a watchdog alarm set value WDWARNINT interrupt register;
WDFEED by writing to the register 0x55 and 0xAA order to enable the watchdog;
To prevent a watchdog event, the watchdog must be fed again before it reaches zero at the watchdog counter. If a
A watchdog window value is set, feed the dog must also go through after the watchdog counter value again.
Watchdog timeout can check flag (the WDTOF) to determine
set if the watchdog reset condition has been generated. WDTOF flag must be cleared by software.
DOG Watchdog Register (WDFEED - 0x4000 0008)
Writing this register 0xAA, then writes the value of the WDTC 0x55 watchdog timer reload. If the set
Set a good watchdog overflow mode, the operating watchdog will start running. After the WDEN bit of WDMOD,
They must also complete a valid feed sequence, and then to produce a watchdog reset.
Before the watchdog really started. The watchdog
ignores the error of the dogs
After the watchdog startup, if the next operation after the write registers 0xAA to WDFEED
WDFEED than writing 0x55 to register, but access to any register a watchdog, it will cause immediate reset /
Interrupted. In the feed sequence, the second one of PCLK cycles after the watchdog register will generate a reset incorrect access.
In the feed sequence process should disable interrupts. If an interruption occurs during the feed sequence, it will produce a suspension bar
Matter.
/* 关中断 */
LPC_WDT->FEED = 0xAA; /* 喂狗 [1] */
LPC_WDT->FEED = 0x55;
/* 开中断 */
4
1
/ * Disable interrupts * /
2
LPC_WDT -> the FEED = 0xAA ; / * DOG [1] * /
3
LPC_WDT->FEED = 0x55;
4
/ * Open interrupt * /
WDT interrupt
NVIC watchdog interrupt channel 16 occupied, interrupt enable register is used to control ISER NIVC channel interrupt enable.
When ISER0 [0] = 1, the channel 16 interrupt is enabled, i.e., the watchdog interrupt is enabled.
IPR interrupt priority register is used to set the priority of interrupt NIVC channel. IPR5 [7: 3] is used to set the preferred channel 16
First, the priority that is the watchdog interrupt
WDT interrupt flag can not be cleared by software, only by hardware reset to zero.
Therefore, when the WDT interrupt occurs, can only be returned by disabling the WDT interrupt the way.
Examples of Use
The use of the watchdog timer within the microcontroller enters an error state in a reasonable period of time to reset.
The watchdog
is enabled, if the user program is not the dogs (i.e., to the watchdog timer reload timer value) within a predetermined period of time,
It will create a watchdog event. Watchdog events cause a device reset (if ready beforehand settings).
4 includes a watchdog timer prescaler and divide a 24-bit counter (count).
Gatekeeper
minimum timing of dog timer interval (T WDCLK × 256 × 4) , the maximum timing interval (TWDCLK × 2 24 × 4) , two
Who are multiples of 4 TWDCLK ×
Instructions:
the watchdog timer constant reload value WDTC register.
set the operation mode in WDMOD watchdog timer register.
If required window type operation, should be set in the watchdog time value WDWINDOW window register.
alarm interrupt if required, should be provided for generating a register WDWARNINT watchdog alarm
Interrupt value.
by sequentially writing 0x55 and 0xAA WDFEED to start the watchdog register.
To avoid watchdog event, before decreasing to 0 in the watchdog timer should re - feed the dog ‖. Such as
If a program has been set up through a window value, it should be after the watchdog counter exceeds this value
Again - feed the dog ‖.
If the watchdog timer is set to lead to when an event occurs when a watchdog reset and the counter is zero, then when the watchdog event
When the situation occurs, it will cause the CPU reset, and load the program counter and the stack pointer (from the external reset vector table
The same conditions). Determining whether the system can be reset by watchdog by checking the watchdog timeout flag (WDTOF).
WDTOF flag must be cleared by software.
If the watchdog timer is set to generate an alarm interrupt, then when the value in the counter register as WDWARNINT
When values are defined to match, it will generate an interrupt.
Watchdog mode register (WDMOD-0x4000 0000)
WDMOD register to control the operation of the watchdog WDEN bit by a combination of bits and RESET. have to be aware of is,
WDMOD feed the dog must register before any changes to take effect.
4 includes a watchdog timer prescaler and divide a 24-bit counter (count). Down counter
minimum value is 0xFF
Lead to window watchdog reset:
In the case where the watchdog is enabled, if the wrong feed sequence will immediately cause watchdog reset.
If not overridden in a programmable timeout period, the internal reset chip.
Window Watchdog operating modes:
Window Watchdog triggered interrupts:
Before the watchdog timeout period (by programming) selectively generates an alarm interrupt.
The correct method to feed the dog
WDFEED value written to the register 0xAA and 0x55 to enable the watchdog timer will reload the WDTC
If the via
through the WDMOD register the Watchdog, running the watchdog This starts
WDWINDOW- window watchdog timer register (WDWINDOW-0x4000 0018)
WDWINDOW WDTV register determines the maximum value allowed in the process of the dogs. If the value is not reached in the WDTV
Prior to this maximum has completed a valid feed sequence, the watchdog event occurs.
WDWINDOW reset to the maximum possible WDTV value, and therefore not affected by this window.
Watchdog Alarm Timer Interrupt Register (WDWARNINT-0x4000 0014)
WDWARNINT register determines the count value of the watchdog generates watchdog timer interrupts. When the watchdog timer counter
When the value of the set value WDWARNINT match, will in the next clock period after WDCLK
Generate an interrupt.
Watchdog timer constant register (WDTC-base + -x04)
WDTC register determines the time-out value of the watchdog timer. Whenever the feed sequence is generated, WDTC constants will be
The watchdog timer is reloaded. Once reset, it would be pre-loaded 0x00 00FF. If a write of less than 0xFF
Value, the system will be charged WDTC register 0x0000 00FF. Thus the minimum time-out interval is TWDCLK × 256 × 4.
If WDMOD WDPROTECT bit register 1, then the watchdog counter is less than WDWARNIN
Before WDWINDOW and try to change the value of WDTC will lead WDTOF and watchdog reset flag is set.
WDTC ----------------------------------------- window timeout value - the value of the initial installation
The segment DOG, watchdog reset
WDWINDOW ------------------------------ window minimum, allowing the dogs after
The segment DOG, watchdog timeout value reload
WDWARNIN -------------------------------- window warning value, after triggering an interrupt
The segment DOG, watchdog reset
0x00 00FF ----------------------------------- timeout trigger a watchdog
reset
DOG time error or error method, will cause the window watchdog
reset
WDTV Watchdog Timer Value. The watchdog timer register is read out of the current
value.
Watchdog by reading the current count value, it is determined whether the timing of the dogs
WWDT_Init(WDT_TIMEOUT); /* 初始化 WDT */
WWDT_Enable(ENABLE);
WWDT_SetMode(WWDT_RESET_MODE, ENABLE);
WWDT_Start(WDT_TIMEOUT);
WWDT_Feed(); /* 喂狗 */
5
1
WWDT_Init ( WDT_TIMEOUT ); / * initialize WDT * /
2
WWDT_Enable(ENABLE);
3
WWDT_SetMode(WWDT_RESET_MODE, ENABLE);
4
WWDT_Start(WDT_TIMEOUT);
5
WWDT_Feed (); / * * DOG /