Nested Vectored Interrupt Controller (NVIC)
Brief introduction
Nested Vectored Interrupt Controller (NVIC) is an internal device Cortex-M3 processor, which is close to the CPU core
Coupled together to complete the response to the interrupt, the interrupt latency is reduced, so that the latest occurrence of the interrupt processing can be efficiently obtained.
NVIC memory mapped registers in a manner to access, in addition to containing the interrupt control registers and control logic outside,
NVIC also contains SysTick timer and debugging control module.
LPC178x / 177x series Cortex-M3 processor supports 41 and 32 nested vectored interrupt programmable interrupt priority.
In addition, NVIC also supports a nonmaskable interrupt (NMI) input.
NVIC access address is 0xE000 E000, all NVIC interrupt control / status registers can only be privileged under
access. But there is one exception - the software triggers an interrupt register can be accessed in order to generate a software interrupt at the user level. All in
OFF control / status word register may press / half word / byte access mode, only by special function register MRS, MSR
Or CPS instructions to access.
characteristic
LPC178x / 177x series NVIC Cortex-M3 processor module characteristics are as follows:
Nested Vectored Interrupt Controller, ARM Cortex-M3 is an integral member;
closely linked with the kernel interrupt controller that supports low latency interrupt;
can control the system and abnormal peripheral interrupt;
LPC178x / 177x of NVIC supports 41 interrupt vectors;
32 programmable interrupt priority levels, with priority hardware shield;
repeatable positioning of the vector table;
nonmaskable interrupt;
software interrupt function.
Interrupt Source
Table 4.61 lists each corresponding to a peripheral interrupt source. Each peripheral device may have one or several line connected to
NVIC, a plurality of interrupt sources may share a common interrupt line.
Further, NVIC also process non-maskable interrupt (NMI). In order to make the operation signal from the external NMI,
NMI should be functionally connected to the associated device pins (P2 [10] / EINT0n / NMI). When the access pin to a logic
1, to an NMI operation.
Register Description
Interrupt signal can be divided into two types of peripheral interrupt and exception system, NVIC send
The main memory comprises a group control register, status register, suspend setting / clear register enable / disable register, priority
Setting register, status register, and active special function registers.
Each interrupt in the NVIC has a number of related registers:
enable and disable register;
suspend setting and clearing registers;
priority registers;
active register.
In addition, the following registers also have some effect on the interrupt handling:
Exception Mask Register (PRIMASK, FAULTMASK and The BASEPRI)
Vector Table Offset Register;
Software Trigger Interrupt Register;
packet priority register.
Interrupt enable and disable
Cortex-M3 interrupt enable and disable control using separate registers. If enabled an interrupt to be sent to the ISER
Register corresponds to writing a "1"; and if a disable interrupt, need to write "1" to the corresponding bit register ICER. Send to ISER / ICER
Register to write "0" is invalid.
ISER / ICER is a 32-bit read / write access to the register, each bit of an interrupt control enable / disable. Register bit description
As described in table 4.62. LPC178x / 177x series Cortex-M3 chip supports 41 nested interrupts, you only need to use
ISER0 / ICER0 and ISER1 / ICER1 two pairs of registers.
Since the first 16 abnormal number has been assigned to the system abnormalities, and therefore the initial abnormal peripheral interrupt number is 16.
Operation Example
Timer 0 and external interrupt 0 interrupt enable and disable operations. Timer 0 interrupt ID TIMER0_IRQn = 1,
External Interrupt 0 Interrupt ID EINT0_IRQn = 18.
NVIC->ISER0 = (1 << ((uint32_t)(TIMER0_IRQn) & 0x1F)); /* 使能 Timer0 中断 */
NVIC->ISER0 = (1 << ((uint32_t)(EINT0_IRQn) & 0x1F)); /* 使能 EINT0 中断 */
NVIC->ICER0 = (1 << ((uint32_t)(TIMER0_IRQn) & 0x1F)); /* 除能 TIMER0 中断 */
NVIC->ICER0 = (1 << ((uint32_t)(EINT0_IRQn) & 0x1F)); /* 除能 EINT0 中断 */
1
The NVIC -> ISER0 = ( . 1 << (( uint32_t ) ( TIMER0_IRQn ) & 0x1F )); / * Interrupt Enable Timer0 * /
2
The NVIC -> ISER0 = ( . 1 << (( uint32_t ) ( EINT0_IRQn ) & 0x1F )); / * Interrupt Enable EINT0 * /
3
The NVIC -> ICER0 = ( . 1 << (( uint32_t ) ( TIMER0_IRQn ) & 0x1F )); / * disable TIMER0 interrupt * /
4
The NVIC -> ICER0 = ( . 1 << (( uint32_t ) ( EINT0_IRQn ) & 0x1F )); / * disable interrupts EINT0 * /
Pending interrupts and clear
When an interrupt occurs, if one or more occurs, the interrupt can not respond immediately, is suspended.
processor is processing a high priority anomalies;
processor is processing the same priority exception;
The interrupts are masked.
Pending interrupt can "set interrupt pending register (the ISPR)" and "Pending Interrupt Clear Register (the ICPR)"
To access.
ISPR / ICPR and ISER / ICER similar register set, a total of eight pairs, listed in Table 4.63. Its usage and ISER / ICER
Register identical. You can modify the register to suspend or interrupt clear a pending interrupt.
The user can modify the ISPR interrupt pending register may be cleared by modifying the interrupt pending register ICPR.
Operation Example
External interrupt 0 Timer 0 interrupts and suspend and clear operation.
NVIC->ISPR0 = (1 << ((uint32_t)(TIMER0_IRQn) & 0x1F)); /* 手动挂起 Timer0 中断 */
NVIC->ISPR0 = (1 << ((uint32_t)(EINT0_IRQn) & 0x1F)); /* 手动挂起 EINT0 中断 */
NVIC->ICPR0 = (1 << ((uint32_t)(TIMER0_IRQn) & 0x1F)); /* 清除 TIMER0 中断挂起状态 */
NVIC->ICPR0 = (1 << ((uint32_t)(EINT0_IRQn) & 0x1F)); /* 清除 EINT0 中断挂起状态 */
1
The NVIC -> ISPR0 = ( . 1 << (( uint32_t ) ( TIMER0_IRQn ) & 0x1F )); / * * Timer0 interrupt pending manual /
2
The NVIC -> ISPR0 = ( . 1 << (( uint32_t ) ( EINT0_IRQn ) & 0x1F )); / * Interrupt Manual EINT0 pending * /
3
The NVIC -> ICPR0 = ( . 1 << (( uint32_t ) ( TIMER0_IRQn ) & 0x1F )); / * Clear TIMER0 interrupt pending state * /
4
The NVIC -> ICPR0 = ( . 1 << (( uint32_t ) ( EINT0_IRQn ) & 0x1F )); / * clear the interrupt pending EINT0 * /
priority
Interrupt priority register. These registers may be assigned a priority of each interrupt, and the interrupt priority field contains.
Operation Example
Of the priority group, set the external interrupt 0
priority.
SCB->AIRCR = (0x05FA) | (0x05 << 8) ； /* 优先级在位 5 处分组 */
NVIC->IPR4 = ( 0x01<< 3) << 16 ； /* 外部中断 0 的优先级寄存器位于 IPR4[23:16] 字段 */
1
SCB of -> AIRCR = ( , 0xFA05 is ) | ( 0x05 << . 8 ) ; / * set disposition priority bit 5 * /
2
NVIC->IPR4 = ( 0x01<< 3) << 16 ； /* 外部中断 0 的优先级寄存器位于 IPR4[23:16] 字段 */
LPC178x/177x 系列 Cortex-M3 芯片支持 41 个向量中断，IPR0~IPR10 为有效寄存器。
活动状态
每个外部中断对应在活动状态寄存器（IABR）都有一个状态位。处理器开始执行中断服务
例程，中断相关的活动位就被置“1”，中断退出该活动位被清“0”。若当前中断在执行服务例
程期间被高优先级的中断抢占，其活动状态也依然为“1”。
IABR 寄存器组描述如表 4.67 所列。IABR 寄存器为 32 位只读寄存器。LPC178x/177x 系列
Cortex-M3 芯片支持 41 个向量中断，IABR0~IABR1 为有效寄存器。
IABR0 寄存器是只读寄存器，可以读取前 32 个外设中断的有效状态。如表 4.68。IABR 的
位会在相应的中断服务程序正在执行时被置位。其它的中断可以通过 IABR1 寄存器来读取其有
效状态。
中断处理
中断建立完整过程如下：
① 系统启动后，设置优先级分组寄存器。缺省情况下分组位为 0，即 7 位抢占优先级、1
位子优先级。
② 如果需要重定位向量表，需要先将硬 fault 和 NMI 服务例程的入口地址写到新表项所在
的地址中。
③ 如果需要重定位向量表，配置向量表偏移量寄存器，使之指向新的向量表。
④ 建立中断向量，即从向量表中取出对应服务程序的入口地址。由于向量表可能进行重定
位，建议先读取向量表偏移量寄存器的值，再根据该中断在表中的位置，计算出服务例程入口
地址。若一直使用 ROM 中的向量表，则无需此步骤。
⑤ 为该中断设置优先级。
⑥ 使能中断。
如果将应用代码存储在 ROM 中，并且不需要修改异常服务程序，可将整个异常向量表存
储在 ROM 的起始区域（0x0000 0000）。在此情况下，向量表的地址偏移量一直为零，并且向
量表已经存在 ROM 中。此时，中断建立的过程可大大简化，只需三步：
① 系统启动后进行优先级分组。
② 设定中断优先级。
③ 使能中断。
由于优先级分组不当会产生不可预知的后果。一般情况下，建议使用默认分组即可，此时
中断建立仅需两步，如图 4.27 所示。其中阴影部分是需户进行软件设置，在软件设置完毕后，
一旦有中断请求信号，Cortex-M3 处理器硬件将自动响应，开始执行入栈、取向量、运行中断
服务函数以及中断退出等操作。