06- Notes: LPC1788- timer

Outline

LPC178x / 177x series Cortex-M3 has four programmable 32-bit timer / counter, each having capture, compare match with the function. Timer is used to the peripheral clock (PCLK) and counted, and the counter for counting an external pulse signal, may be to choose to interrupt or performs other operations at predetermined times, by which the value of four match registers. It also contains four capture inputs, used to capture the instantaneous value of the timer when the input signal changes, may be selected to generate an interrupt.

NOTE: four timer / counters, except for the peripheral base address identical to the other. Four timers capture least two inputs and two outputs match

Out, and a plurality of pins can be selected. Timer 2 leads to matching all four outputs.

characteristic

L 32-bit timer / counter with a programmable prescaler 32;

 counter or timer operation;

Each timer  contains two 32-bit capture channels, capturing the instantaneous value of the timer when the input signal changes. also may

Select to generate an interrupt;

 4 32-bit match register, allows the following operations:

- continuous operation matching, match with optional interrupt generation;

- stop the timer runs match with optional interrupt generation;

- reset the timer match with optional interrupt generation;

 There are four registers corresponding matching external output, these outputs have the following functions:

- match to a low level;

- to match the high level;

- inverted match levels;

- Do nothing on match.

LPC178x / 177x series Cortex-M3 timer / counter function member is mainly composed of three parts:

1. Counting section

The timer may be a clock PCLK source, after PCLK frequency-divides the input counter, counts them. Further LPC178x / 177x series Cortex-M3 may be counted from the CAP external pulse input pin of the external pulse.

2. Matching section

Match register holds the matching value from 0 to 3, when a match value matches a current count value, the matching control register register (MCR) is set, the timer control operation, an interrupt signal may be generated. When a match occurs, the register EMR will control the corresponding matching output pin MATn specific signal.

3. Capture function part

When a valid signal is present on pin CAPN capture (i.e., capture signal), the current value will be saved to the counter capture register register CRn, and may generate an interrupt

Register Description

1. Interrupt register T [0/1/2/3] IR

Interrupt register contains 4 bits for matching an interrupt, four bits for capture interrupt. If an interrupt is generated to the IR should bit is set, and 0 otherwise. IR write to the corresponding bit will reset the interrupt. Written 0 invalid. Clear match interrupt timer also clears the corresponding DMA request.

LPC_TIM0->IR = 0xff;  /*  清除定时器 0 的全部中断标志 */

 
LPC_TIM0 -> IR  =  0xff ;   / * Clear all Timer 0 interrupt flag * /

2. Timer control register T [0/1/2/3] TCR

Timer control register (TCR) is used to control timer / counter operation

LPC_TIM0->TCR = 0x01; /*  启动定时器 0

 
LPC_TIM0 -> the TCR  =  0x01 ; / * start timer 0

3. Counter control register T [0/1/2/3] CTCR

Count Control Register (the CTCR) is used to select between the timer mode and the counter mode, the counter mode selection pin count and an edge of the

When the selected mode as the operation mode counter, the input of the CAP PCLK rising edge of each clock (manufactured by the CTCR : 3 sampling bit 2 is selected). After two consecutive sample values of the inputted comparison CAP, may be identified following one event: rising, falling, rising level constant / falling CAP input or selected. If the identified events and CTCR register [1: 0] corresponding to a selected event, the value of the timer counter register is incremented by one.

When the external pulse counter, the efficiency of the process will receive some limitations. Since CAP identifying a selected input side along a need to use two consecutive clock PCLK rising edge of the input frequency of the CAP thus can not exceed half of the frequency of PCLK one. Therefore, in this case, the same below a high / low duration CAP pin is not less than 1 / (2PCLK).

LPC_TIM0->CTCR = ( 0x02 << 0 ) |  /*  计数器，在 CAP 的下降沿递增 TC */
( 0x01 << 2 ); /*  选择 CAP0.1

 
LPC_TIM0 -> the CTCR  = ( 0x02  <<  0 ) |   / * counter is incremented on the falling edge of CAP TC * /
( 0x01  <<  2 ); / * Select CAP0.1

4. Timer counter T [0/1/2/3] TC

TC (Timer Counter) is both a timer counter and the timer counter by external, herein referred to as a timer counter

5. Prescaler register T [0/1/2/3] PR

6. Prescaler counter T [0/1/2/3] PC

7. Match register (MR0-MR3)

Match register values are continuously compared with the count value of the timer. When the two values are equal to automatically trigger a corresponding action. These actions generate an interrupt, or stop the timer resets the timer counter. Action performed by the control register MCR.

8. Match Control Registers T [0/1/2/3] MCR

DMA operations

Each timer when matching EM0 and EM1 (transition from 0 to 1) can cause a DMA request

Set the timer interrupt

LPC178x series Cortex-M3 contains four 32-bit timers, each timer can generate eight types of interrupts: 4 -way match interrupt, 2 capture interrupt by reading the interrupt flag register (TnIR) to distinguish the type of interrupt

Timer 0 Interrupt NVIC occupied channel 17, the timer 1 interrupt NVIC occupied channel 18, the timer interrupt 2 accounted for 19, the timer interrupt 3 with 20 channels occupied NVIC NVIC channel, the interrupt enable register is used to control ISER NIVC interrupt channel is enabled. When ISER0 [1] = 1, the channel 17 interrupt is enabled, i.e., the timer 0 interrupt is enabled; when ISER0 [2] = 1 , the channel 18 interrupt is enabled, i.e., a timer interrupt is enabled; when ISER0 [3 ] = 1, the interrupt enable passage 19, i.e., the timer 2 interrupt enable; when ISER0 [4] = 1, the channel 20 interrupt is enabled, i.e., the timer interrupt 3 is enabled.

IPR interrupt priority register is used to set the priority of interrupt channel NVIC. IPR0 [15:11] Channel 17 is used to set the priority, i.e. the timer 0 interrupt priority; IPR0 [23:19] is used to set the priority channel 18, i.e., the timer 1 interrupt priority; IPR0 [31:27] is used to set the priority of the channel 19, i.e. the timer 2 interrupt priority; IPR1 [7: 3] is used to set the priority of the channel 20, i.e., the timer interrupt priority 3

When the timer interrupt priority setting and When enabled, if a match occurs interrupt or capture interrupt, the interrupt is triggered

LPC178x series Cortex-M3 may capture timer interrupt or interrupt match

1. Interrupted match

The timer counts not generate an interrupt on overflow, but you can generate an interrupt when a match. Each timer has four matching registers (MR0 ~ MR3), matching can be used to store the value when the current count value of the timer value TC is equal to the matching MR, can generate an interrupt.

2. Capture interrupt

When the specific capture signal appears on the capture pin CAP timer can generate an interrupt.

Cortex-M3 LPC178x series of four 32-bit timers, each having a 2-way capture, 4 compare match timer is the incremental count, overflow but does not generate an interrupt flag, but only

Compare match or capture by input into the interrupt flag is generated