stm32 study notes a detailed analysis of the DMA

  1, DMA Profile

  DMA (Direct Memory Access: Direct Memory Access) is a data transfer can greatly reduce the workload of the CPU mode.

  CPU has transferred data, compute, transfer control program, and many other functions, but actually transfer data (especially the transfer of large amounts of data) can not require CPU intervention. A copy of the data desired peripherals such as a peripheral to B, as long as a data path to the two kinds of peripherals, plus some transfer of control member to complete copy of the data.

  DMA is conceived based on the above design, its role is to transfer large amounts of data to solve the problem of excessive consumption of CPU resources. DMA allows the CPU with more focus on a more practical operation - computing, control and the like.

  2, DMA works

  DMA is the direct action of the transmission data, and link removed conventional data transmission requires the participation of CPU registers, four cases mainly to data transmission, but is essentially the same, are from a region of memory to memory transfer another area (memory unit is a memory data register peripheral nature). Data transfer four cases are as follows:

  Peripheral to memory

  Memory-to-peripheral

  Memory to memory

  Peripheral-to-peripheral

  When the user set parameters, mainly related to a source address, destination address, three data transfer amount, the DMA controller will initiate a data transfer, the end points of the remaining data volume is zero (the transmission cycle is not the case). In other words as long as the remaining data volume is not zero, and the DMA is activated state, then the data transfer occurs.

  3, DMA would not affect the operation of the CPU

  In the X86 architecture system, when a DMA operation (assuming we copy a file from disk to U disk), DMA actually occupy part of the system bus cycle time. In other words, before the DMA is not turned on, the system bus may be used entirely CPU; When the DMA is turned on, the system bus to allocate some time for the DMA, DMA and CPU at the same time to ensure the operation. So obviously, DMA reduces CPU speed.

  In the controller STM32, Cortex-M3 chip architecture, the bus structure has been greatly optimization, the DMA bus occupation another, and do not conflict with the CPU system bus. That is, using DMA will not affect the speed of the CPU.

  Two, STM32 DMA structure

  1, the main characteristics of the DMA

  ● 12 independent configurable channels (requests) the DMA1 has seven channels, DMA2 five channels

  ● Each channel is connected directly to dedicated hardware DMA requests, each channel also supports software trigger. These functions by

  Software to configure.

  ● can be programmed by software provided in the request priority among the seven (a total of four levels: high, high, medium, and low), if the phase

  Isochronous determined priority (priority 0 request 1 to the request, and so on) by hardware.

  ● independent transmission width of the source and destination data area (byte, halfword, word-wide), packing and unpacking process simulation. Source and destination

  Address must be aligned to the data transfer width.

  ● support circular buffer management

  ● Each channel has three event flag (half DMA transfer, the DMA transfer is completed and the DMA transfer an error), the three event flag

  Into a single logical or interrupt request.

  ● transfer between the memory and the memory

  ● peripherals and memory, memory and peripherals transmission

  ● flash memory, SRAM, peripherals SRAM, APB1 APB2 and AHB peripherals can be used as source and destination access.

  ● programmable number of data transmission: Maximum 65536

  The following is a functional block:

  

 

  2, two DMA controllers structure

  ① DMA1 controller

  

 

  ② DMA2 controller

  

 

  3, DMA register list

  

 

  ① interrupt class

  DMA_ISR: DMA interrupt status register

  DMA_IFCR: DMA interrupt flag will be cleared register

  Description: DMA1, DMA2, respectively, a set of registers.

  ② control transmission class

  DMA_CCRx: DMA Channel Configuration Register x

  DMA_CNDTRx: DMA channels x number of data registers

  DMA_CPARx: DMA Channel x Peripheral Address Register

  DMA_CMARx: DMA Channel x memory address register

  Description:

  1> Each channel has a set of registers.

  2> DMA_CPARx, DMA_CMARx is no difference, they can address storage peripherals, memory address. DMA_CPARx, DMA_CMARx name just get up there is a difference only.

  4, STM32 DMA's work features

  Necessary condition ① DMA data transfer

  The remaining transmission data is larger than 0

  DMA channel transfer enable

  通道上DMA数据传输有事件请求

  前两者都好理解,对于第三点确实需要详细的解释,请看下边的三条。

  ② 外设到XX方向的传输

  假设是ADC到存储器的数据传输,显然ADC的DMA传输的源地址是ADC的数据寄存器。并不是说只要DMA通道传输使能后,就立即进行数据传输。只有当一次ADC转化完成,ADC的DMA通道的传输事件有效,DMA才会从ADC的数据寄存器读出数据,写入目的地址。当DMA在读取ADC的数据寄存器时,同时使ADC的DMA通道传输事件无效。显然,要等到下一次ADC转换完成后,才能启动再一次的数据传输。

  ③存储器对XX的DMA传输

  因为数据是准备好的,不像ADC还需要等待数据到位。所以,不需要对应通道的事件。只要使能DMA数据传输就一直传输,直到达到设定的传输量。

  example:

  1.内存到内存

  DMA传输请求一直有效

  2.内存到串口

  DMA传输请求一直有效

  一种解释:

  存储器对存储器的置位,就相当于相应通道的事件有效。 对应通道的事件有效和存储器对存储器的置位,就是传输的触发位。每次传输的事件置位一次,完成一次传输。如果是由外设引发的DMA传输,则传输完成后,相应传输事件会置为无效,而存储器对存储器的传输,则一次传输完成后,相应事件一直有效,直至完成设定的传输量。           

  ④外设以DMA方式工作时,能否再以软件方式进行操作?

  有一点是肯定的,当外设以DMA方式正在数据传输时,不可能再相应CPU的软件控制命令,否则这不符合逻辑。

  但是,倘若外设仅仅配置成DMA工作方式,但是DMA请求并未产生,数据传输并没有进行。此时,软件控制命令仍然能够对外设进行控制。这是笔者在串口以DMA方式发送数据情形下,所得到的测试结论。

  三、STM32的DMA软件编程

  1、“内存到内存”模式传输

 

  2、利用DMA实现循环传输

  方法1:单次传输模式

  当传输结束时,触发DMA中断,在中断程序中首先失能DMA通道,然后修改该通道的传输数据量。最后重新使能DMA通道,注意只有失能的DMA通道才能成功修改传输数据量。

  方法2:循环传输模式

  当传输结束时,硬件自动会将传输数据量寄存器进行重装,进行下一轮的数据传输。

  四、再谈STM32的DMA传输是否影响CPU的运行速度

  声明:经过笔者测试,当DMA工作在内存到外设的传输和内存到内存的传输时,都不会影响CPU的运行速度。为了给这种现象一个合理的解释,笔者做以下猜测:

  1、S3C2440的DMA传输

  S3C2440的SDRAM是外置的,并且SDRAM的数据线、地址线、控制线总共只有一组。假设DMA传输的方向是内存到外设,当DMA运作时,需要占用SDRAM的三类线才才能实现传输;而与此同时CPU也需要通过这三类线来访问SDRAM来读取程序、读写数据。

  显然,DMA的运行与CPU的运行有交叉点,DMA就会影响到CPU的运行。

  2、STM32的DMA传输

  STM32与S3C2440的区别是很大的,S3C2440是微处理器,RAM外置且空间很大;STM32是微控制器,RAM片内集成且空间较小。此时,ST公司就有可能提升DMA的运作效率,使DMA的工作不影响到CPU的运行。

  外设与外设之间的DMA传输,因为与CPU的运行没有交叉点(CPU的数据流注意是在Flash、内存、寄存器中传输),所以不会影响CPU的运行速度。唯一有可能影响的是外设与内存或者内存与内存之间的DMA传输。

  倘若ST公司的SRAM是一个双口RAM,也就是同时可以由两组接口对RAM进行访问,就可以很好的解决速度影响问题。倘若CPU恒定占有一组接口,而另一组接口留给DMA控制器。那么当外设与内存或者内存与内存之间的DMA传输时,由于不与CPU的访问SRAM接口冲突,所以可以解决速度影响问题。

  但其实偶尔还是会影响的,当CPU访问SRAM的空间和DMA访问SRAM的空间相同时,SRAM势必会对这种情况进行仲裁,这可能会影响到CPU的访问SRAM的速度。其实,这种情况的概率也是很小的,所以即使影响CPU的运行速度,也不会很大。

(DMA专题讲解)
http://www.makeru.com.cn/live/1392_1048.html?s=45051
http://www.makeru.com.cn/live/1392_1020.html?s=45051
stm32 如何用DMA搬运数据
http://www.makeru.com.cn/live/detail/1484.html?s=45051

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Origin www.cnblogs.com/8734ujn/p/11591812.html