ZYNQ Note (6): PL precision timer interrupt

　　Software timer interrupt is difficult to control precisely the position of the edge trigger can be interrupted by interrupting the complete precise timing of PL-PS. PL interrupt generated by the Verilog code so closely integrated processing PS-PL play to their strengths.

 

A, PL lower timer interrupt

1. The actual requirements

 

① rising edge interrupt; 
② high-level width not less than 1us; 
③ interruption counter is clocked 200Mhz; 
④ There are two interrupts: 3ms and 0 .5 ms

 

2.Verilog interrupt code

1  // *********************************************** ***************************
 2  // *** name: genintr3ms05ms.v
 3  // *** author: xianyu_FPGA
 4  // *** blog: https://www.cnblogs.com/xianyufpga/ 
5  // *** date: 2019-08-10
 6  // *** description: 3ms and 0.5ms delay precision
 7  // ** ************************************************** ********************** 
. 8  
. 9  
10  Module1 genintr3ms05ms
 . 11  // ================== <port > ================================================= = 
12  (
 13 // the INPUT ----------------------------------------- 
14  the INPUT   Wire                  CLK, / / clock, 200Mhz 
15  INPUT   Wire                  RST, // reset active high
 16  // Output ----------------------------- ----------- 
17  the Output  REG                   intr3ms, // 3ms interrupt 
18  the Output  REG                   intr05ms               // 0.5ms interrupt 
19  );
 20  //================== <parameter> ============================= ===================== 
21 is  Parameter CNT3MS_END = 600000             ;
 22 is  Parameter CNT05MS_END = 100000             ;
 23 is  Parameter PULSEW = 200 is                ; // interrupt high maintenance time
 24  @ ================== <signal> ============================= ===================== 
25  REG   [ 23 is : 0 ] cnt3ms;
 26 is  Wire                         add_cnt3ms;
 27  Wire                        end_cnt3ms          ;
28 reg  [23:0]                 cnt05ms             ;
29 wire                        add_cnt05ms         ;
30 wire                        end_cnt05ms         ;
31 
32 //==========================================================================
33 //==    0.5ms延时
34 //==========================================================================
35 always @(posedge clk) begin
36     if(rst)
37         cnt3ms <= 0;
38     else if(add_cnt3ms) begin
39         if(end_cnt3ms)
40             cnt3ms <= 0;
41         else
42             cnt3ms <= cnt3ms + 1;
43     end
44 end
45 
46 assign add_cnt3ms = 1;
47 assign end_cnt3ms = add_cnt3ms && cnt3ms== CNT3MS_END-1;
48 
49 always @(posedge clk) begin
50     if(rst) begin
51         intr3ms <= 0;
52     end
53     else if(end_cnt3ms) begin
54         intr3ms <= 1;
55     end
56     else if(add_cnt3ms && cnt3ms==PULSEW-1) begin
57         intr3ms <= 0;
58     end
59 end
60 
61 //==========================================================================
62 //==    3ms延时
63 //==========================================================================
64 always @(posedge clk) begin
65     if(rst)
66         cnt05ms <= 0;
67     else if(add_cnt05ms) begin
68         if(end_cnt05ms)
69             cnt05ms <= 0;
70         else
71             cnt05ms <= cnt05ms + 1;
72     end
73 end
74 
75 assign add_cnt05ms = 1;
76 assign end_cnt05ms = add_cnt05ms && cnt05ms== CNT05MS_END-1;
77 
78 always @(posedge clk) begin
79     if(rst) begin
80         intr05ms <= 0;
81     end
82     else if(end_cnt05ms) begin
83         intr05ms <= 1;
84     end
85     else if(add_cnt05ms && cnt05ms==PULSEW-1) begin
86         intr05ms <= 0;
87     end
88 end
89 
90 
91 
92 endmodule

 

3.PL interruption encapsulated into a private IP

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Two, ZYNQ hardware interrupt usage

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