PubMed | Composition Principle [Chapter 2] Data Representation and Operation

PubMed | Composition Principle [Chapter 2] Data Representation and Operation

I. Number system and coding

a. Carry counting system and its mutual conversion

1. Integer part converted from decimal to binary:Pay attention to the high and low order
   
2. Decimal to binary conversion:Watch out for high-status sorting

b. BCD code

BCD code:It is Binary-Coded Decimal, which is a binary-coded decimal number

1. 8421 yards

Code 8421:That is, each number from 0 to 9 is expressed one by one with 4-bit binary numbers; among them, the 8421 code is also called the right code , counting from left to right, the weight of the first 1 is 8; the weight of the second 1 is 4; the third 1 has a weight of 2; the fourth 1 has a weight of 1;

decimal	5	+	8	=	1	3
binary	0101	+	1000	=	0001	0011

2. The remaining 3 yards

3 yards left:It belongs to the unrighted code , which is based on the 8421 code, adding $(3{)}_{10}$, which is binary $(0011{)}_2$

3. 2421 yards

Code 2421:Same as the 8421 code, both belong to the weighted code , but different from the 8421 code, counting from right to left, each 1 has a weight of 2421

 

c. Unsigned integer representation and operation

1. Express

1. All binary bits are value bits, no sign bit , the iiThe bit weight of$i$$2^{i-1}$
2. $n$ bit unsigned integer represents the range$0\sim 2^n-1$ , overflow if exceeded
3. The minimum number is all 0s; the maximum number is all 1s

2. Operation

1. addition:Starting from the lowest bit, add bit by bit, and carry to a higher bit
2. Subtraction:
   1. "Minuend" remains unchanged, all bits of "subtrahend" are reversed bit by bit, the last bit is +1 (that is, complement code), subtraction becomes addition
   2. Starting from the lowest bit, add bit by bit, and carry to a higher bit.
       

d. Representation and operation of signed integers

1. Original code

For $n+1$ -bit machine word length:

1. The highest bit is the sign bit, "0/1" corresponds to "positive and negative"; the remaining bits are value bits, which represent the absolute value of the true value
2. Indicates the range $-(2^n-1)\le x\le 2^n-1$
3. The truth value 0 has two forms , $[+0{]}_{}=0,00000000;[-0{]}_{}=1,00000000$

Disadvantages: The sign bit cannot participate in the operation, and complex hardware circuits need to be designed to process it

2. Inverse code

On the basis of the original code: the positive number remains unchanged; the sign bit of the negative number remains unchanged, and the value bit is reversed

3. Complement

1. Machine way:Original → Inverse → Complement ( inverse code to complement code: positive numbers remain unchanged, negative numbers + 1 at the end )
   

2. Manual calculation method:Original → complement
   Positive numbers remain unchanged; negative numbers find the first 1 from right to left, and all the digits to the left of this 1 are reversed bit by bit;
   the same method is used to convert complement codes to original codes, positive numbers remain unchanged, and negative numbers move from right to left Find the first 1 on the left, and all the value bits to the left of this 1 are bitwise inverted
   

3. Here is a method that I summed up to calculate the truth value directly from the complement of negative numbers:
   See the blue part in the lower right corner of the above picture

   1. Find the first 1 from right to left
   2. The binary weight corresponding to all 0s to the left of this 1 + the binary weight corresponding to this 1 = true value

4. Two's complement addition:Starting from the lowest bit, add bit by bit (including the sign bit), and carry to a higher bit

   

5. Two's complement subtraction:

   1. The "minuend" remains unchanged, and the "subtrahend" is all bitwise inverted ( including the sign bit ), and the last bit is +1
   2. Subtraction becomes addition, starting from the lowest bit, adding bit by bit, and carrying to a higher bit

4. Frameshift

Frameshift:On the basis of complement code, the sign bit is reversed; Note: only positive numbers can be represented

5. Comparison of original negative complement and frame-shift characteristics

1. Conversion relationship:
   

2. Indicates the range:
   

3. Several codes are used to represent integers:
   

e. Representation and operation of fixed-point decimals

1. Fixed Point Decimal vs Fixed Point Integer

Note: The first digit of the fixed-point decimal is the sign bit, that is, the digit before the decimal point; the fixed-point decimal cannot be represented by shifting

2. Addition of fixed-point decimals

Same as fixed-point integer addition: start from the lowest bit, add bit by bit (including the sign bit), and carry to a higher bit;

3. Subtraction of fixed-point decimals

Same as fixed-point integer subtraction: "minuend" remains unchanged, all bits are reversed bit by bit, the last bit is +1, subtraction becomes addition

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II. Calculation method and circuit

a. Basic computing components

1. Logical operations

• with|or|not
  

• AND NOT| OR NOT| DIFFERENT AND NOT| SAME OR
  

• Implement XOR gates with NOR combinations
  

• Simplify logical expressions

  • Priority: with > or
  • 电影律: $A(C+D)=AC+AD$
  • Associativity: $ABC=A\left(BC\right)$ ; $A+B+C=A+(B+C)$
  • 反演律: $\overline{A+B}=\overline{A}\cdot \overline{B}$; $\overline{A\cdot B}=\overline{A}+\overline{B}$

2. One-bit full adder

The function implemented by a full adder is an addition on a binary bit, not only combining the binary bits of the current two addends, but also combining the carry from the previous binary bit.

• Addition result $S_i$: See if there are even or odd 1s in the input (the binary bits of the two addends and the carry of the previous bit)
  $S_i=A_i\oplus B_i\oplus C_{i-1}$
• Carry to high bit $C_i$: If there are at least two 1s in the input, the carry is 1
  $C_i=A_i{B}_i+(A_i\oplus B_i)C_{i-1}$
  The first item represents that the binary bits of both addends are 1,
  and the second item represents that only one of the two basic bits is 1, and the carry from the lower bit is 1

Expressed in a logic circuit diagram:

3. Serial Adder

Serial adder: It is only composed of a one-bit full adder. The two addends are sent to the full adder bit by bit for operation. This is serial. If the operand is nn $n$ bits, the adder will perform$n$ operations.

4. Parallel adder with serial carry

Parallel adder with serial carry: put $When\; n$ full adders are connected in series, two$The\; result\; of\; the\; addition\; of\; n$ -bit binary numbers

can be seen from the figure. The disadvantages are obvious. Since the input of each stage includes the carry of the previous bit in addition to the binary numbers of the two addends itself, the input of each stage Addition depends on the upper level.

5. Parallel adder with parallel carry

The parallel adder with parallel carry is actually playing some tricks on a serial basis. As mentioned earlier, due to the limitation of carry $C_{i-1}$, so we have $C_i$ 进行展开:
$$\begin{array}{rl}& C_i=A_i{B}_i+\left(A_i\oplus B_i\right)C_{i-1}\\ & C_i=A_i{B}_i+\left(A_i\oplus B_i\right)\left(A_{i-1}{B}_{i-1}+\left(A_{i-1}\oplus B_{i-1}\right)C_{i-2}\right)\\ & C_i=A_i{B}_i+\left(A_i\oplus B_i\right)\left(A_{i-1}{B}_{i-1}+\left(A_{i-1}\oplus B_{i-1}\right)\left(A_{i-2}{B}_{i-2}+\left(A_{i-2}\oplus B_{i-2}\right)C_{i-3}\right)\right)\end{array}$$
When expanded to $C_0$When , the overall $C_i$can be determined directly, because each bit of $A_i$ $B_i$Already, $C_i$It is also known, then you can directly calculate the carry $C_i$
We repeat $G_i=A_i{B}_i$  $P_i=A_i\oplus B_i$
C i = A and B i + ( A i ⊕ B i ) C i − 1 = G i + P i C i − 1 C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 C 1 = G 2 + P 2 G 1 + P 2 P 1 C 0 C 3 = G 3 + P 3 C 2 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 C 0 C = G 4 + P 4 C 3 = G 4 + P 4 G 3 + P 4 P 3 G 2 + P 4 P 3 P 2 G 1 + P 4 P 3 P 2 P 1 C 0 \begin{aligned} &C_{ i}=A_{i}B_{i}+\left(A_{i}\plus B_{i}\right) C_{i-1}=G_{i}+P_{i}C_{i-1} \\&C_{1}=G_{1}+P_{1} C_{0} \\&C_{2}=G_{2}+P_{2} C_{1}=G_{2}+P_{2} G_{1}+P_{2} P_{1} C_{0} \\&C_{3}=G_{3}+P_{3} C_{2}=G_{3}+P_{3} G_{2 }+P_{3}P_{2}G_{1}+P_{3}P_{2}P_{1}C_{0}\\&C_{4}=G_{4}+P_{4}C_{3 }=G_{4}+P_{4} G_{3}+P_{4} P_{3} G_{2}+P_{4} P_{3} P_{2} G_{1}+P_{4} P_{3} P_{2} P_{1} C_{0} \end{aligned}​Ci​=Ai​Bi​+(Ai​⊕Bi​)Ci−1​=Gi​+Pi​Ci−1​C1​=G1​+P1​C0​C2​=G2​+P2​C1​=G2​+P2​G1​+P2​P1​C0​C3​=G3​+P3​C2​=G3​+P3​G2​+P3​P2​G1​+P3​P2​P1​C0​C4​=G4​+P4​C3​=G4​+P4​G3​+P4​P3​G2​+P4​P3​P2​G1​+P4​P3​P2​P1​C0​​
Draw a circuit diagram:

6. Complementary addition and subtraction

1. XY corresponds to two addends or minuend and subtrahend respectively
2. set $sub$ , set to 1 if it is subtraction, and set to 0 if it is addition
3. 当 $sub$ is 0, that is, when adding, Y directly enters the adder through the multiplexer
4. 当 $sub$ is 1:
   1. Y will go through the NOT gate first, and perform bitwise inversion on all the bits on Y
   2. At the same time, $sub$ as 1, also as$C_{i-1}$into the adder
   3. Invert all the bits of Y and then +1 to complete the operation from XY to X+(-Y)
      

7. Flag generation

 

b. Shift operations of fixed-point numbers

1. Arithmetic shift

2. Logical shift

• Logical right shift:Fill high bits with 0, discard low bits
• Logical left shift:Fill low bits with 0, discard high bits

3. Cyclic shift

c. Multiplication of fixed-point decimals

1. Original code multiplication

• The sign bit is processed separately, sign bit $=x_s\oplus y_s$
• The absolute value of the numeric digits is multiplied:

1. First review the components of several calculators:
   
2. We now want to calculate: $[x{]}_{}=1.1101,[y{]}_{}=0.1011,x\cdot y$
3. First change the sign bit of the multiplicand, namely x, to 0, take the absolute value, and put it into the general register XXThe multiplier in$X$
   , that is, y, the sign bit also takes 0, takes the absolute value, and puts it into the multiplication quotient register$MQ$ accumulatorACC
   ACC$ACC$ all set to 0;
   
4. Looking at the multiply quotient register $MQ$ , the first one is$1$
   then we go to accumulatorACC ACCAdd general-purpose registerXX$to\; A$$C$$C$Multiplicand XXin$X$$X$
   then accumulator$ACC$ and multiplication quotient register$Mand\; Q$ logically shift right together: the high bit is complemented with$0$ , discard low bits
5. Then repeat the fourth step, still $1$ , so we add to the accumulator$ACC$ first add general registerXXMultiplicand in$X$$ACC$ and$MQ$ logical shift right together:
6. Continue to repeat the fourth step, but this time it is $0$ , if encounter$0$ , accumulator$ACC$ does not add anything, and directly adds to the multiplication quotient register$MQ$ logical shift right
7. Repeat the fourth step until the multiplication quotient register $The\; sign\; in$$MQ$ is shifted to the last bit, and it can be stopped. AtACC ACC
   needs to be$The\; first\; bit\; of\; ACC$ , that is, the sign bit is changed to the first sign bit$=x_s\oplus y_s$
   Then accumulator $ACC$ and multiplication quotient registerMQ MQThe numbers combined by$M$$and\; Q\; are\; the\; result\; of\; the\; final\; product$
   
8. Simplifying the above process into a hand calculation process is like this:
   

2. Two's complement multiplication

• Complement multiplication is similar to original multiplication, but there are differences:
  
• In the operation of two's complement multiplication:
  • The machine word length of all registers is unified $n+2$ bits, using double sign bit to represent complement code.
  • Multiply Quotient Register $In$$MQ$ , the single sign bit is used to represent the multiplier's complement, and the last machine bit is placed in the auxiliary bit, which is initially 0
  • Auxiliary bits - $The\; lowest\; bit\; in\; MQ$ = 1,$(ACC)+[x{]}_{}$
    Auxiliary bits - $The\; lowest\; bit\; in\; MQ$ = 0,$\left(ACC\right)+0$
    auxiliary bit -$The\; lowest\; bit\; in\; MQ$ = -1,$\left(ACC\right)+[-x{]}_{}$
  • After addition, $ACC$ andMQ MQArithmetic shift right with$M\; and$$Q$
  • Move to the right until it is originally placed in the multiplication quotient register MQ MQAfter the sign bit of the multiplier of$M$$Q\; ,\; one\; more\; addition\; has\; to\; be\; performed$
  • Last accumulator $ACC$ and multiplication quotient register$MQ$ together form the final product (signed bit)
    

d. Division of fixed-point decimals

1. Original code division operation

1-1. Recovery remainder method

• General register $X$ store divisor
  accumulator$ACC$ stores the dividend Multiplication
  quotient register$MQ$ storage result quotient
• The sign bit handles $x_s\oplus y_s$
• Put the corresponding divisor and dividend into the general register $X$ , accumulator$ACC$ , multiplication quotient register$Set\; MQ$ to 0
  

1. Every round, direct no-brained quotient $1$
   
2. Find the remainder: $(ACC)-\left(divisor\right)\to ACC$
   
3. Discover $In\; ACC$ , the remainder is a negative number, and the quotient is changed to$0$
   
4. Change the quotient to $After\; 0$ ,$ACC$ should also be changed back, so$\left(ACC\right)+\left(divisor\right)\to ACC$ , this step is called recovering the remainder
   
5. Then $ACC$ and$MQ$ overall logical shift left
   
6. Repeat steps 1~5 until the multiplication quotient register $All\; machine\; bits\; in$$MQ$ have a definite quotient
   
   
   
   
   
   
   
   
   
7. Finally got the result
   
8. Summary: Look at the flow chart
   

1-2. Alternate addition and subtraction method (non-recovery remainder method)

• main idea:
  
• Overall process:
  
  

2. Complementary division operation

• Essence:
  
• There is a classic question:
  
  • If you don't study this question deeply, you can choose BB directly$B$ , should be the multiplication and division of complement code, the key step is that the sign bit participates in the operation
  • If you dig deeper:
    • What is subtraction: the absolute value of the minuend is greater than the absolute value of the subtrahend
    • Dividing the same sign:

      find the remainder	Enough to reduce	business	Not enough to reduce	business
      subtraction	Divisor and remainder have the same sign	1	divisor and remainder	0

    • Get along with different signs:

      find the remainder	Enough to reduce	business	Not enough to reduce	business
      addition	divisor and remainder	0	Divisor and remainder have the same sign	1

    • Such as: dividend -3, divisor -2 and +2, enough to subtract
      • $-3with-2samenumber\Rightarrow -3-(-2)=-1\Rightarrow Remainderanddivisorhave\; thesamesign\Rightarrow Quotient1$
      • $-3with+2differentsigns\Rightarrow -3+(+2)=-1\Rightarrow Remainderanddivisorwithdifferentsigns\Rightarrow Quotient0$

e. Certificate type and type conversion in C language

f. Data storage and arrangement

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III. Representation and operation of floating point numbers

a. Representation of floating point numbers

b. Addition and subtraction of floating point numbers