An embedded system components
1.1 hardware subsystems
(1) embedded processor
It is the core component of the system. Representative ARM processor, as shown; MIPS PowerPC MC68000
(2) Peripherals
SRAM RAM Flash memory
Ethernet communication RS232 SPI
LCD display
Debugging, etc.
1.2 software subsystem
2 embedded processor
2.1 The basic structure
Kernel data stream
·
REG : 37 [registers their function in the user programming division,
-
31 general-purpose 32-bit registers (including a program counter (PC pointer))
-
6 32bits status register (the operating state to the operating state of the CPU and the program identification)
a total of 37 registers.The six status registers in the ARM file name are:
the CPSR (Current Program State the Register),
in SPSR_svc,
SPSR_abt,
SPSR_und,
SPSR_irq,
SPSR_fig.
32 × 32-bit barrel shifter , left / right by n bits, n cyclic shift and arithmetic shift right by n bits and so can be done on, can effectively reduce a delay time shift.
High-speed multiplier
An arithmetic logic unit the ALU : numerical and logical calculations, made up of several latches, adders, logic functions, and the results of two zero detection logic operation.
The control unit : PC program counter (instruction recorded in the memory position) IR instruction register
2.2 Evaluation
(1) Power
MIPS / W, how many millions of instructions per unit time per watt instruction execution
Shutdown shutdown mode, Dormant, Run Mode with MPE powered off, Run Mode with MPE disabled; Full Run Mode Standby Standby Mode: by the impact of operating mode (Cortex A9)
(2) code storage density
(3) integration
(4) Display Acceleration
(5) Performance, Efficiency
Dhrystones integer arithmetic and logical performance tests (MIPS) Whetstone floating point performance test (MFLOPS)
The number and size of compiled code algorithm executed per second EEMBC
2.3 arm history
The company offers only arm arm series RISC processor core for semiconductor production and marketing company, intel, freescale, philips atmel sharp sumsung
The first 91 years of nuclear arm6
93 arm7
Business Model
2.4 Applications
2.5 Features
(1) RISC technology common feature
- Large number of registers, data and instruction Cache,
- Register operations
-
- Fixed-length instruction format, to facilitate water
- Flexible and simple addressing modes
- Kernel small, low power, low cost
(2) ARM system, especially technology
- Thumb 16bits and supports instruction set ARM 32bits bis
- load / store instructions to transfer data Bulk
- Three-address instruction format
- The data processing instruction includes an arithmetic logic unit, and a shift processing
2.6 arm architecture development
v1 address space 64MB (26bits)
V3 address space 4GB (32bits)
V4 increases 16bits Thumb instruction setARM7 8 9 STRONG ARM
V5 increase instruction, Jazelle ARM9, ARM10 XSCALE
V6 SIMD multi-processing ARM 11
V7 supports Thumb-2 technology Cortex-A8 A9(v7-A)
name
assembly line
development of
Pipeline Workflow
CORTEX -A9
Kernel structure
2.7 Work status
It supports different types of instructions and data
ARM state 32bits (Word) arm instruction
Thumb state 16bits (half-word) Thumb instruction
Jazelle state of the variable length Java instruction units Byte
ThumbEE state
after reset ARM
Switch
Current Program Status Register
Jump instruction BX
2.8 Processor operating modes
CPSR Model is determined by the position,
ARMv7 theory has nine mode (3 privilege level PL0-PL2).
When we said to be seven, they usually are omitted from both MON and HYP, which is mainly used for MON trust OS (secure OS), and HYP mainly used hypervisor (virtualization).
- User: non-privileged mode, perform most of the tasks in this mode, the normal program execution state
- FIQ: When a high priority (FAST) will enter this mode generates an interrupt, or for high-speed data transmission channel processing
- IRQ: When a low priority (normal) will enter this mode generates an interrupt, the interrupt handling versatile
- Supervisor (svc): When the reset instruction is executed, or soft interrupt will enter this default mode. The protected-mode operating system
- Abort (abt): When the access exception will enter this mode, the instruction prefetch termination (termination instruction) ./ data access termination, the virtual storage can be used for storage and protection
- Undef: Undefined instruction executed when this mode is entered
- User-privileged mode and a mode register using the same set: System
除User（用户模式）是Normal（普通模式）外，其他6种都是Privilege（特权模式）。
Privilege中除Sys模式外，其余5种为异常模式（Exception Modes）。
各种模式的切换，可以是程序员通过代码主动切换（通过写CPSR寄存器）；
也可以是CPU在某些情况下自动切换。 各种模式下权限和可以访问的寄存器不同。
2.9 memory format
ARM architecture allows the use of conventional memory and I / O devices for a wide variety of memory system design.
(1) address space
ARM architecture using two 32 single byte, linear address space. The unsigned byte address as the look, the range 0 to 232-1.
Linear combination of bytes starting at address zero
32bits 4Bytes
4GB
(2) Memory Format
(1) big-endian format
Low byte of word data in upper address
eg
7-0bit 15-8bit 23-16bit 31-24bit the corresponding byte in the address
(2) little endian
Small small
is the default mode
(3) ARM memory structure
ARM processor with someAnd Data Cache Instruction Cache, butWith no on-chip RAM and ROM chip. RAM and ROM required for the system (including Flash) throughExternal bus.
Since the address range of the system is large (232 = 4GB),
the sheet further with someThe memory management unit MMU (Memory Management Unit)
ARM processor architecture also allows for an external PCMCIA.
(4). Memory mapped I / O
ARM system uses memory mapped I / O. I / O port using a particular memory address, when loading from addresses (for input) or to store these addresses (for output), I / O completion function.
Load and store execution control functions can also be used instead of or in addition to the normal input or output functions.
However, the behavior of the memory mapped I / O locations is typically different from a normal memory position to the desired behavior.
For example, the continuous loading from a normal memory position twice, each time return the same value. For memory-mapped I / O locations, 2nd loading the return value may be different from the return value of the 1st load.
