Introduction startup mode
Most Boot Loader contains two different operating modes: "boot loader" mode and "download" mode, this distinction makes sense only for developers. However, the end-user's point of view, the role of Boot Loader is used to load the operating system, but there is no difference between the so-called boot loader mode and download mode of operation.
Boot loader (Boot loading) mode: This mode is also called "independent" (Autonomous) mode. That Boot Loader from a solid-state storage devices on the target operating system is loaded into RAM to run the entire process and no user intervention. This mode is the normal operating mode of Boot Loader, so when Hou embedded products released, Boot Loader obviously have to work in this mode.
Download (Downloading) mode: In this mode, Boot Loader on the target machine via a network connection or other serial communication means to download files from the host (Host), such as: downloading the kernel image and root file system image and the like. Downloaded from the host file is typically saved Boot Loader to a first target machine RAM, then is written to FLASH BootLoader solid state storage devices based on the target machine. Boot Loader This mode is usually used when the first kernel and root file system is mounted; in addition, the subsequent use of the system will update the Boot Loader This mode of operation. Work provides a simple command line interface in Boot Loader usually in this mode to its end users.
UBoot so powerful Boot Loader supports both operating modes, and allows the user to work between these two modes
Switch.
Most bootloader is divided into stage 1 (stage1) and Phase 2 (stage2) two parts, uboot is no exception. Code that relies on the CPU architecture (e.g., CPU initialization code, etc.) are usually placed in Stage 1 and generally implemented in assembly language, and Phase 2 is usually implemented in C language, which can implement complicated functions, but there are better readability and portability.
Phase 1 Introduction
The code is usually placed uboot stage1 start.s file, which is written in assembly language, the main code is the following:
Defining the entry
Due to an executable Image must have an entry point, and there is only one global entry, usually the entrance on the 0x0 ROM (Flash) of
Address, therefore, must inform the compiler so that it knows the entrance, the work can be done by modifying the linker script.
- board/crane2410/uboot.lds: ENTRY(_start) ==> cpu/arm920t/start.S: .globl _start
- uboot code area (TEXT_BASE = 0x33F80000) defined in the board / crane2410 / config.mk
Set up exception vectors
| _start: b |
reset |
@ 0x00000000 |
| ldr |
pc, _undefined_instruction |
@ 0x00000004 |
| ldr |
pc, _software_interrupt |
@ 0x00000008 |
| ldr |
pc, _prefetch_abort |
@ 0x0000000c |
| ldr |
pc, _data_abort |
@ 0x00000010 |
| ldr |
pc, _not_used |
@ 0x00000014 |
| ldr |
pc, _irq |
@ 0x00000018 |
| ldr |
pc, _fiq |
@ 0x0000001c |
When an exception occurs, execution cpu / arm920t / interrupts.c defined interrupt handler.
Set CPU model for SVC mode
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr, r0
Close Watchdog
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ldr r0, =pWTCON
mov r1, # 0x0 @ Samsung to adjust the settings according to the manual. str r1, [r0]
Ban all interrupts
mov r1, #0xffffffff
LDR r0, = INTMSK
str r1, [r0]
# if defined(CONFIG_S3C2410) ldr r1, =0x3ff
LDR r0, = INTSUBMSK
str r1, [r0]
Arranged to CPU frequency
Default frequency FCLK: HCLK: PCLK = 1: 2: 4, the default value of FCLK 120 MHz, which is the recommended value S3C2410 manual. ldr r0, = CLKDIVN
mov r1, #3
str r1, [r0]
Setting CP15
After setting CP15, invalid instruction (I) Cache and data (D) Cache, MMU and prohibit Cache.
cpu_init_crit:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 / * failed I / D cache, see S3C2410 manual appendix 2-16 * / mcr p15, 0, r0, c8, c7, 0 / * invalid TLB, see S3C2410 manual Appendix 2-18 * /
/*
* Prohibit MMU and caches, see Appendix 2-11 S3C2410 manual
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, # 0x00002300 / * clear the bits 13, 9: 8 (--V- --RS)
* Bit 8: Disable System Protection
* Bit 7: Disable ROM Protection
* Bit 13: exception vector table base address: 0x0000 0000
*/
bic r0, r0, # 0x00000087 / * Clear bits 7, 2: 0 (B --- -CAM)
* Bit 0: MMU disabled
* Bit 1: Alignment Fault checking disabled
* Bit 2: Data cache disabled
* Bit 7: 0 = Little-endian operation
*/
orr r0, r0, #0x00000002 /* set bit 2 (A) Align, 1 = Fault checking enabled */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache, 1 = Instruction cache enabled
*/
mcr p15, 0, r0, c1, c0, 0
Configuring memory control registers
Configure memory control registers, the specific value of the register is usually provided by the development board vendor or hardware engineer. If you are very familiar with Fan Weisheng bus cycle and peripheral chips, you can own determined settings file UBOOT is the board / crane2410 / lowlevel_init. S, the file contains lowleve_init block. explained in detail and the register setting value, see 3.2.2 AXD starting point 5 disposed in a development board.
mov ip, lr
bl lowlevel_init
mov lr, ip
Installation U-BOOT make stack space
The following code not only started from Nand Flash code snippet makes sense to start from the code Nand Flash, does not make sense. because
Nand Flash from the execution code UBOOT move to the RAM, the completion code 2.1.9.
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
...
#endif stack_setup:
ldr r0, _TEXT_BASE / * start address of code section * / sub r0, r0, #CFG_MALLOC_LEN / * allocate dynamic memory area * /
sub r0, r0, #CFG_GBL_DATA_SIZE / * UBOOT global data storage boards * /
#ifdef CONFIG_USE_IRQ
/ * Assign IRQ and FIQ stack space * /
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, # 12 / * 3 left word Abort * /
BSS segment cleared 0
clear_bss:
ldr r0, _bss_start / * start address BSS segment * / ldr r1, _bss_end / * BSS segment end address * /
mov r2, # 0x00000000 / * BSS segment set to 0 * /
clbss_l: str r2, [r0] / * Clear BSS cycle segment * / add r0, r0, # 4
cmp r0, r1
was clbss_l
Move Nand Flash Code
From the Nand Flash, copy the data to the RAM, is done by copy_myself block, the block is explained in detail: 3.1 Part VII.
#ifdef CONFIG_S3C2410_NAND_BOOT
bl copy_myself
@ jump to ram
ldr r1, =on_the_ram add pc, r1, #0
nop nop
1: b 1b @ infinite loop
on_the_ram:
#endif
Into the C code portion
ldr pc, _start_armboot
_start_armboot: .word start_armboot