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statements are statements task and function are used to define the design verilog tasks and functions, and a task by defining function, program modules have been able to greatly decomposed smaller and any function, which is more easy to understand and debug. In the design, a block may often be used repeatedly in different locations in some large programs, invoked by defining task and function to save the amount of code to simplify the structure of the program, but also easy to understand.

1. different functions and tasks

First macro to look at different points functions and tasks, and then took questions have to learn direction.

Different points tasks and functions:

A function can be shared only with the master module simulation time units , and their task definition simulation time units.
Function can not start the task, the task can start other tasks and functions.
Function must have at least one input variable, and the task can not or multiple variables of any type.
Function returns a value, but the task does not return a value .

Note that object, the response function is to return the value of the input signal by a function value, while the object of a wide variety of tasks, can result calculated values, these values can result output by the called task or output bus port sent. When using Verilog HDL module function is to treat it as an expression of the kind of operator ( serious experience ah, the operator, it would just result ), the result of this operation is to perform the function's return value, the return value can be used in other operations.

2. task declaration statement

Previously said that once the objective function is the function returns a value required for other expressions.

2.1 task definitions

The syntax for defining tasks are as follows:

task<任务名>

<端口及数据类型声明语句>

<语句1>

<语句2>

…………

<语句n>

endtask

Various statements in the mission, consistent module block its syntax Vierlilog of usage.

Transfer calls and variables 2.2 task

Mission call:

<Task name> (Port 1, Port 2, .. ..., n-port);

The following examples illustrate how the definition of tasks and sub-tasks call:

Task definition:

task my_task;

    input  a,b;  //可以有输入
    inout  c;

    output d,e;  //可以有输出

     <语句>

       ….
     c = fool;   //
     d = foo2;   //对输出变量赋值
     e = foo3;

endtask

Task call:

my_task(v,w,x);

Is the task calls between variables (v, w, X) and defined task I / O variables (a, b, c) one to one , when the task started by v and w are assigned to the incoming variable a and b, whereas when the output of the task is completed and after the assigned by c x,

3. function declaration statement

The foregoing describes it, the purpose of calling functions is the need to return a value other expressions for

3.1 syntax defined functions

      function<返回值的类型或范围>(函数名)；   //返回值的类型可选，默认返回值为一位寄存器类型数据

         <端口说明语句>

        <变量类型说明语句>

       begin

                <语句>

                     ………

        end

       endfunction

NOTE: <return type or range of values> This is an optional, default values such as a register bit type data is returned

for example

Here is an example of the actual procedure, function given to illustrate the actual function

And how to call the righteous.

task or function