Each Quad contains two LC based PLL, referred to as a Quad PLL (qpl0 and qpl1). Any QPLL can share the same in a four channel serial transceivers, but not shared by the other four channels. When the rate is above the line at the operating range CPLL operating channel, it is necessary to use QPLL0 / 1. gtye3 / 4_common primitive encapsulated gty qpll0 / 1, and must be instantiated when using qpll.
When the channel moves exceeding 16.375 GB / s, QPLL0 must GTREFCLK0, QPLL1 must GTREFCLK1. QPLL0 / 1 serial output for each transceiver in the same channel of a Quad Tx and Rx clock divider block provides the reference clock to control the generation of serial and parallel data clock PMA and PCS blocks used.
2-13 illustrates a conceptual view QPLL0 / 1 architecture. Before the input clock is fed to the phase frequency detector, which is divided by a factor m. Multiplication decision feedback divider ratio n of the VCO. For the linear velocity is less than 28.1 GB / s to support fractional-N divider, where n is a combination of factors effective than adding the fractional part. QPLL0 / 1
output frequency depends on QPLL [0/1] CLKOUT_RATE setting. When QPLL [0/1] CLKOUT_RATE set to HALF, the VCO output frequency is half the frequency. When set to FULL, the same frequency as the output frequency of the VCO. A lock indicator comparison reference clock and the VCO feedback clock to determine whether the frequency lock has been achieved.
QPLL0 / 1 VCO operate in two different bands. Table 2-12 describes the rated operating range of the band. For more information, see UltraScale and UltraScale + equipment data sheets
Wizard and select the appropriate band provided qpll based on application requirements.
Equation 2-3 shows how to determine the PLL output frequency (GHz). For the linear velocity higher than 28.1 GB / s, ignoring the fractional part.
Formula 2-4 shows how to determine the line rate (GB / s). d represents the value of the Tx or Rx channel clock divider block. D effective setting, see page 45 Table 2-9.
Equation 2-5 shows how to determine the feedback divider equation given 2-3 fractional part.
In an example 10.3125G, Fpllclkin = 64.453125M, N = 160, M = 1, QPLL_CLKOUTRATE = 2, D = 1.
fpllclkout=64.453125*160/2=5.15625G
flinerate=fpllclkout*2/D=10.3125G
