summarize.
S3C2440 chip comprising the GPIO controller, UART, I2C controller and the like, the CPU register is used to control the operation of the input or output pin, the actual operation is the operating register memory address, so references to the memory controller. The CPU sends the address to the memory controller, memory controller address, the address will be sent to different modules, e.g. GPIO controller, serial port controller. Address is usually issued by the CPU is not sent to off-chip devices.
But the type of memory device is an exception, memory devices including, memory, network card, orflash and so on. The CPU address signal and data to the memory-class device directly through an address bus and a data bus.
The above types of equipment are unified addressing data CPU (NAND FLASH not participate CPU unified addressing). SDRAM, NOR flash, NIC common address bus, a data bus, in order to avoid mutual interference between them, introducing a chip select pin, CS. The memory controller according to the address issued by the CPU, the device needs to be accessed is determined, and the chip select pin is provided for the device is high. I.e., the device is selected, the chip select pin the other devices are low. Only chip select pin is high level of equipment before they can work.
The memory address distribution map, can be deduced, each corresponding address space cs of 128m (2 ^ 27). That requires at least 27 address lines.
When an orientation cpu address, the selected address from the controller apparatus cs pin, and sends the information 27 address lines.