External Memory Interface (EMIF)

What is used in actual work is the DSP of model TMS320C6678, and communicates with FPGA through EMIF interface.

Since the EMIF interface is relatively simple, this paper designs it from the perspective of FPGA as the slave end of the EMIF interface. The reference manual is KeyStone Architecture External Memory Interface (EMIF16) User Guide - May 2011

EMIF interface between FPGA and DSP debugging
EMIF interface
DSP external device connection interface EMIF
DSP study notes----EMIF (external memory interface)

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1. Overview

The external memory interface (External Memory Interface, EMIF) is mainly used to connect with parallel memory, these memories include SDRAM, SBSRAM, Flash, SRAM memory, etc.

It can also be connected with external parallel devices, including parallel A/D, D/A converters, dedicated chips with asynchronous parallel interfaces, and can be connected with FPGA, CPLD, etc. through EMIF.

The EMIF interface can use different interface signals according to different memory types. For FPGA, it can be regarded as a kind of external memory of DSP for communication.

2. Timing Description

The timing diagram is as follows, which is divided into three stages: Setup, Strobe and Hold. The duration of the three phases depends on the Async 1 Config Register

2.1. Read Timing

The read timing is as follows, EMIFD data is sampled on the first rising edge of the HOLD phase

2.2. Write Timing

3. EMIF Slave Design Spec

RTL logic design of Slave side of EMIF.

External Memory Interface (EMIF) RTL design - verilog