Section 3 Module Structure
3.1 Module Introduction
Module (module) is Verilog'sbasic unit of description, are external ports used to describe the functionality or structure of a design and communicate with other blocks .
A module can be conceptually equivalent to a device, such as calling a general device (AND gate, tri-state gate, etc.) or a general macro unit (counter, ALU, CPU), etc. Therefore, one module can be called in another module, and a circuit design can be composed of multiple modules. The design of a module is only a certain level of design in a system design, and a variety of modeling methods can be used for module design.
The basic design unit of Verilog is the "module". The modular design makes the system look more organized and facilitates simulation and testing. Therefore, the design idea of the whole project is module within module, which is unfolded sequentially from top to bottom. In the design of a project, each module implements a specific function, and the modules can be nested hierarchically. When designing a large-scale digital circuit, it can be divided into small modules of different sizes, each small module implements a specific function, and finally the overall function is realized by calling the sub-module from the top-level module. This is Top-Down design thinking . This book is mainly based on the Verilog hardware description language, and the module is the basic description unit of Verilog, which is used to describe the function and structure of each design, as well as the external interface for other modules to communicate.
A module has five main parts: port definition, parameter definition (optional), I/O description, internal signal declaration, function definition .Modules always start with the keyword module and end with the keyword endmodule. Its general grammatical structure is as follows:
3.2 Module name and port definition
Lines 1 to 5 declare the name of the module and the input and output ports. Its format is as follows: module module name (port 1, port 2, port 3, ...); where the module starts with module and ends with endmodule. The module name is the unique identifier of the module . It is generally recommended that the module name be named with a name that can describe its function, and the module name and the file name are the same.
The port of the module represents the input and output port names of the module, and is also the identification of its contact port with other modules .
3.3 Parameter Definition
Line 8 parameter definition is to replace constants with symbols to increase code readability and modifiability. This is an optional statement, which can be omitted if it is not used. The general format of the parameter definition is as follows :
parameter DATA_W = x;
3.4 Interface definition
Lines 9 to 12 are I/O (input/output) descriptions, and the ports of the module can be input ports, output ports or bidirectional ports . The description format is as follows.
Input port : input [signal bit width-1: 0] port name 1;
input [signal bit width-1: 0] port name 2;
……;
Output port : output [signal bit width-1: 0] port name 1;
output [signal bit width-1: 0] port name 2;
……;
Bidirectional port : inout [signal bit width-1: 0] port name 1;
inout [signal bit width-1: 0] port name 2;
……;
3.5 Signal types
Lines 14 to 17 define the type of signal. These signals are the signals used in the module, and the wire and reg type variables related to the port ( ie wire network type and register type ). It is declared as follows:
reg [width-1: 0] R variable 1, R variable 2 ...;
wire [width-1: 0] W variable 1, W variable 2...;
If no signal type is defined,The default is wire type, and the signal bit width is 1 .
3.6 Functional Description
Lines 21 to 31 are the function description part. in the moduleThe most important part is the logical function definition part, there are three ways to generate logic in a module.
- Use the "assign" statement, as described
- Describe a two-input AND gate: assign a = b & c. For detailed functions, see the section "Functional Description - Combination Logic".
- Use the "always" block. That is, the sequential logic and combinational logic introduced earlier.
- Module instantiation. See the "Module Instantiation" section for detailed functions.
3.7 Module instantiation
The design of the digital system generally adopts a top-down design method, which can divide the system into several functional modules, and each functional module is further divided into sub-modules of the next layer. The design of each module corresponds to a module, and each module is designed as a Verilog HDL program file. Therefore, a structured design is adopted for the top-level modules of a system, that is, the top-level modules call each functional module separately .
A module can be referenced within another module, thus creating a hierarchy of descriptions. The module instantiation statement has the following form:
module_nameinstance_name(port_associations) ;
Signal ports can be associated by location or name, but the association methods cannot be mixed. The port association form is as follows: port_expr // by position. .
PortName (port_expr) // Pass name.
suggestion: Please use name association in the instantiated port mapping , so that it is not easy to make mistakes when the called module pin changes. In the instantiation, some pins may not be used, and blank processing can be used in the mapping, such as:
The input of the input pin floating port is high-impedance Z. Since the output pin is floating, the output pin is discarded.。