Table of contents
1. Experimental environment equipment
1. Hardware
FPGA: Xiaomeige AC101-EDA development board
Ultrasonic ranging sensor: HC_SR04
DuPont line
2. Software
Fourth ll
2. Module design
Use the development board to drive the ultrasonic detection module (HC_SR04), and display the measured data on the digital tube on the development board.
3. Principle of Ultrasonic Module
The main technical parameters
1. Working voltage: DC-5V
2. Static current: less than 2mA
3. Level output: high 5V
4. Level output: bottom 0V
5. Induction angle: no more than 15 degrees
6. Detection distance: 2cm - 450cm
Ultrasonic principle
-
Use IO port TRIG to trigger ranging, and give a high level signal of at least 10us
-
The module automatically sends 8 square waves of 40khz, and automatically detects whether there is a signal return
-
When there is a signal return, a high level is output through the IO port ECHO, and the duration of the high level is the time from the ultrasonic wave to its return. Test distance = (high level time * speed of sound (340M/S))/2
This module is easy to use. One control port sends a high level of more than 10US, and then it can wait for the high level output at the receiving port. Once there is an output, the timer can be started, and when the port becomes low level, it can read The value of the timer, at this time, is the time of this distance measurement, and the distance can be calculated. Such continuous periodic measurement can reach the value of your mobile measurement
Principle of distance measurement
Module Timing
The above timing diagram shows that you only need to provide a pulse trigger signal of more than 10uS, and the module will internally send out 8 40kHz periodic levels and detect echoes. Once an echo signal is detected, an echo signal is output
The pulse width of the echo signal is proportional to the measured distance. From this, the distance can be calculated by transmitting the signal to the received echo signal time interval
Formula: uS/58=cm or uS/148=inch; or: distance = high level time * speed of sound (340M/S) / 2
It is recommended that the measurement period be above 60ms to prevent the influence of the transmitted signal on the echo signal
System architecture design
It is mainly divided into six modules:
1. Trig_driver output control module: mainly responsible for controlling 10μS continuous level output, according to the system design, wait for 10μS every 1s on average, and output 10μS continuous level after the signal is stable
2. Echo_driver signal input conversion: input signal processing, echo level output is proportional to the detection distance, and the distance data is output by calculation
3. Time_counter timing module: through timing, it gives the signal that needs to output level, digital tube segment selection displacement or data processing
4. seg_drver digital tube display module: calculate and display the output content of the digital tube in real time
5. HC_SR_top top-level module: connect the above modules together as the top-level module of the system
6. fiter Gaussian filter module: process the data displayed by the digital tube, and use Gaussian filter to reduce the data fluctuation caused by environmental factors
4. Implementation effect and code
Project source code:
https://github.com/vers17/-FPGA-
5. References
https://blog.csdn.net/m0_59161987/article/details/130788410?spm=1001.2014.3001.5502
https://blog.csdn.net/m0_59161987/article/details/130788412?spm=1001.2014.3001.5502
https://blog.csdn.net/qq_47281915/article/details/125592938?spm=1001.2014.3001.5502