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The link initialization and training (Link Initialization & Training) in the PCIe bus is a function completely implemented by hardware, which is at the physical layer in the PCIe architecture. The whole process is automatically completed by the Link Training and Status State Machine (LTSSM), which means that there is basically no data link layer and transaction layer.
A schematic diagram of the location of LTSSM in the PCIe architecture is as follows:
After the system is reset, link training will be performed automatically to achieve the following goals: bit lock (Bit Lock), character lock (Symbol Lock, Gen1 & Gen2 Only), block lock (Block Lock, Gen3 Only), determine the link width (Link Width), lane position inversion (Lane Reversal), signal polarity inversion (Polarity Inversion), link data rate (Data Rate) and lane alignment (Lane-to-Lane De-skew) and other functions.
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The LTSSM (Link Training and Status State Machine) block checks and memorizes what is received on each lane, determines what should be transmitted on each lane and transitions from one state to another. The LTSSM (Link Training and Status Machine) block checks and
memorizes Keep track of what is received on each channel, determine what should be transmitted on each channel, and transition from one state to another.
Link Training and Status State Machine consists of 11 top-level states: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback and Disable. These can be grouped into five categories: Link Training states, Re -Training (Recovery) state, Software driven Power Management states, Active-State Power Management states, Other states. The
link training and state state machine consists of 11 top-level states: Detection, Polling, Configuration, Recovery, L0, L0s, L1, L2, warm reset, loopback and disable. These can be grouped into five categories: link training state, retraining (recovery) state, software-driven power management state, active state power management state, and other states.
The flow of the LTSSM follows the Link Training states when exiting from any type of Reset: Detect >> Polling >> Configuration >> L0. In L0 state, normal packet transmission / reception is in progress. The Recovery State is used for a variety of reasons, such as changing back from a low-power Link state, like L1, or changing the link Bandwidth. In this state, the Link repeats as much of the training process as needed to handle the matter and returns to L0. Power management software can also place a device into a low-power device state forcing the Link into a lower Power Management Link state (L1or L2). If there are no packets to send for a time, ASPM Software may be allowed to transition the Link into low power ASPM states (L0s or ASPM L1). In addition, software can direct a link to enter some other special states (Disabled, Loopback, Hot Reset.)
When exiting any type of reset, the flow of the LTSSM follows the Link Training state: Detect >> Polling >> Configuration >> L0. In the L0 state, normal packet transmission/reception is in progress. There are various reasons to use the recovery state, such as changing back from a low-power link state such as L1, or changing link bandwidth. In this state, Link repeats the training process as many times as necessary to handle the problem before returning to L0. Power management software can also place the device into a low-power device state, forcing the link into a lower power-managed link state (L1 or L2). ASPM software can be allowed to transition the link to a low-power ASPM state (L0 or ASPM L1) if there are no packets to send for a period of time. In addition, the software can also guide the link into some other special states (Disabled, Loopback, Hot Reset).
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11.4. Link Training 11.4. link training
The Physical Layer automatically performs link training and initialization without software intervention. This is a well-defined process to configure and initialize the device's Physical Layer and link so that PCIe packets can be transmitted. If you encounter link training issues, viewing the actual data in hardware should help you determine the root cause. You can use the following tools to provide hardware visibility:
物理层自动执行链路训练和初始化，无需软件干预。这是一个定义明确的过程，用于配置和初始化设备的物理层和链路，以便传输 PCIe 数据包。如果您遇到链路训练问题，查看硬件中的实际数据应该可以帮助您确定根本原因。您可以使用以下工具来提供硬件可见性：
- Signal Tap Embedded Logic Analyzer
Signal Tap 嵌入式逻辑分析仪 - Third-party PCIe protocol analyzer
第三方 PCIe 协议分析仪
You can use Signal Tap Embedded Logic Analyzer to diagnose the LTSSM state transitions that are occurring on the PIPE interface. The ltssmstate bus encodes the status of LTSSM. The LTSSM state machine reflects the Physical Layer's progress through the link training process. For a complete description of the states these signals encode, refer to Reset, Status, and Link Training Signals. When link training completes successfully and the link is up, the LTSSM should remain stable in the L0 state. When link issues occur, you can monitor to determine the ltssmstate cause .You
can use the Signal Tap Embedded Logic Analyzer to diagnose LTSSM state transitions occurring on the PIPE interface. The ltssmstate bus encodes the state of the LTSSM. The LTSSM state machine reflects the progress of the physical layer in the link training process. See Reset, Status, and Link Training Signals for a complete description of the states encoded by these signals. When link training completes successfully and the link comes up, the LTSSM should remain stable in the L0 state. When link problems occur, you can monitor ltssmstate to determine the cause.