Table of contents
TRST-Resets the JTAG TAP controller and the CPU internal debug logic
SRST- Resets the CPU core and peripherals
The following figure is the JTAG pin foot diagram designed by the Trace32 tool for ARM debug:
Among them, the TRST and SRST signals are optional.
TRST-Resets the JTAG TAP controller and the CPU internal debug logic
The Test Reset signal is used for asynchronous reset of the JTAG Test Access Port (TAP). It will reset the state machine of TAP and most of the debug-related registers of the ARM series. From the debugger's perspective, the TRST signal is output from the debugger to the target board. It is active low.
SRST- Resets the CPU core and peripherals
System Reset, active low, used to reset the target system. This signal can also be used by the debugger to detect whether the target processor is in reset state. This signal can be an input or an output.
SYStem.Mode Down
With the debugger disabled, the state of the CPU does not change.
SYStem.Mode Nodebug
Same as down, the debugger is disabled, and the state of the CPU will not change.
SYStem.Mode Prepare
Reset the target processor, which can be achieved by a reset signal (reset line) or a special reset register in the CPU. Afterwards, direct access to the CoreSight DAP interface will be provided. For reset, the reset line must be connected to the debugger.
The debugger will initialize some debug ports (JTAG, SWD, cJTAG) and the CoreSight DAP interface, but will not connect to the CPU. This mode can be used in some scenarios that do not need to debug the CPU or bypass the CPU. The debugger directly passes through the memory bus (memory bus), such as AXI, AHB or APB, and directly through the memory access port of CoreSight DAP, such as:
- The debugger bypasses the CPU and directly accesses physical memory. If the mapping exists, the memory should be initialized before being accessed.
- The debugger accesses peripherals such as configuration registers before stopping the CPU in debug mode. Peripherals may need to be clocked and powered before they can be accessed.
- Third-party software or some special debuggers use the TRACE32 API to access the debug port and DAP through the TRACE32 debugger hardware.
SYStem.Mode Go
Resets the target via the reset line, initializes the debug ports (JTAG, SWD, cJTAG), and starts process execution. For reset, the reset line must be connected to the debug connector
SYStem.Mode Attach
No reset will occur, and the CPU state (running or stopped) will not change. Debug ports (JTAG, SWD, cJTAG) will be initialized. After executing this command, the user process can be stopped, for example, using the Break command.
SYStem.Mode StandBy
Hold the target in reset via the reset line and wait for power to be detected. For reset, the reset line must be connected to the debug connector. Once power is detected, the debugger restores as many debug registers as possible (e.g. on-chip breakpoints, vector capture events, control) and releases the CPU from reset to start process execution. When a CPU power loss is detected, the debugger automatically switches back to standby mode. This allows debugging power cycles, as the debug registers will be restored on power-up. Note: On-chip breakpoints and vector capture events can usually only be set while the CPU is running. To set a software breakpoint, the CPU must be stopped.
SYStem.Mode Up
Reset the target through the reset line, initialize the debug ports (JTAG, SWD, cJTAG), stop the CPU, and enter the debug mode, and the relevant registers are restored to default values. For reset, the reset line must be connected to the debug connector. The current state of all registers is read from the CPU.
Although the author did not find any description about SYStem.Mode Up triggering SRST in the document, in actual use, it can be found that SYStem.Mode Up does trigger SRST.
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